mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
AArch64: enable MISched by default.
Substantial SelectionDAG scheduling is going away soon, and is interfering with Hao's attempts to implement LDn/STn instructions, so I say we make the leap first. There were a few reorderings (inevitably) which broke some tests. I tried to replace them with CHECK-DAG variants mostly, but some too complex for that to be useful and I just reordered them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192282 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -39,6 +39,10 @@ public:
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///
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AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS);
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virtual bool enableMachineScheduler() const {
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return true;
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}
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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@ -7,13 +7,13 @@ define void @test_simple_alloca(i64 %n) {
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%buf = alloca i8, i64 %n
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; Make sure we align the stack change to 16 bytes:
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; CHECK: add [[SPDELTA:x[0-9]+]], x0, #15
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; CHECK: and x0, [[SPDELTA]], #0xfffffffffffffff0
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; CHECK-DAG: add [[SPDELTA:x[0-9]+]], x0, #15
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; CHECK-DAG: and x0, [[SPDELTA]], #0xfffffffffffffff0
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; Make sure we change SP. It would be surprising if anything but x0 were used
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; for the final sp, but it could be if it was then moved into x0.
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; CHECK: mov [[TMP:x[0-9]+]], sp
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; CHECK: sub x0, [[TMP]], [[SPDELTA]]
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; CHECK-DAG: mov [[TMP:x[0-9]+]], sp
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; CHECK-DAG: sub x0, [[TMP]], [[SPDELTA]]
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; CHECK: mov sp, x0
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call void @use_addr(i8* %buf)
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@ -37,13 +37,13 @@ define i64 @test_alloca_with_local(i64 %n) {
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%loc = alloca i64
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%buf = alloca i8, i64 %n
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; Make sure we align the stack change to 16 bytes:
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; CHECK: add [[SPDELTA:x[0-9]+]], x0, #15
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; CHECK: and x0, [[SPDELTA]], #0xfffffffffffffff0
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; CHECK-DAG: add [[SPDELTA:x[0-9]+]], x0, #15
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; CHECK-DAG: and x0, [[SPDELTA]], #0xfffffffffffffff0
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; Make sure we change SP. It would be surprising if anything but x0 were used
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; for the final sp, but it could be if it was then moved into x0.
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; CHECK: mov [[TMP:x[0-9]+]], sp
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; CHECK: sub x0, [[TMP]], [[SPDELTA]]
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; CHECK-DAG: mov [[TMP:x[0-9]+]], sp
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; CHECK-DAG: sub x0, [[TMP]], [[SPDELTA]]
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; CHECK: mov sp, x0
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; Obviously suboptimal code here, but it to get &local in x1
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@ -112,16 +112,16 @@ declare i8* @llvm.stacksave()
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declare void @llvm.stackrestore(i8*)
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define void @test_scoped_alloca(i64 %n) {
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; CHECK: test_scoped_alloca
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; CHECK-LABEL: test_scoped_alloca:
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; CHECK: sub sp, sp, #32
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%sp = call i8* @llvm.stacksave()
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; CHECK: mov [[SAVED_SP:x[0-9]+]], sp
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; CHECK: mov [[OLDSP:x[0-9]+]], sp
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%addr = alloca i8, i64 %n
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; CHECK: and [[SPDELTA:x[0-9]+]], {{x[0-9]+}}, #0xfffffffffffffff0
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; CHECK: mov [[OLDSP:x[0-9]+]], sp
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; CHECK: sub [[NEWSP:x[0-9]+]], [[OLDSP]], [[SPDELTA]]
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; CHECK-DAG: sub [[NEWSP:x[0-9]+]], [[OLDSP]], [[SPDELTA]]
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; CHECK: mov sp, [[NEWSP]]
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call void @use_addr(i8* %addr)
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@ -9,16 +9,16 @@ define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
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%tst1 = icmp ugt i32 %lhs32, %rhs32
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%val1 = select i1 %tst1, i32 42, i32 52
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store i32 %val1, i32* @var32
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; CHECK: movz [[W52:w[0-9]+]], #52
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; CHECK: movz [[W42:w[0-9]+]], #42
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; CHECK-DAG: movz [[W52:w[0-9]+]], #52
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; CHECK-DAG: movz [[W42:w[0-9]+]], #42
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; CHECK: csel {{w[0-9]+}}, [[W42]], [[W52]], hi
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%rhs64 = sext i32 %rhs32 to i64
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%tst2 = icmp sle i64 %lhs64, %rhs64
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%val2 = select i1 %tst2, i64 %lhs64, i64 %rhs64
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store i64 %val2, i64* @var64
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; CHECK: cmp [[LHS:x[0-9]+]], [[RHS:w[0-9]+]], sxtw
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; CHECK: sxtw [[EXT_RHS:x[0-9]+]], [[RHS]]
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; CHECK-DAG: cmp [[LHS:x[0-9]+]], [[RHS:w[0-9]+]], sxtw
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; CHECK-DAG: sxtw [[EXT_RHS:x[0-9]+]], [[RHS]]
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; CHECK: csel {{x[0-9]+}}, [[LHS]], [[EXT_RHS]], le
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ret void
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@ -5,8 +5,8 @@ define i32 @test_floattoi32(float %in) {
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%signed = fptosi float %in to i32
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%unsigned = fptoui float %in to i32
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; CHECK: fcvtzu [[UNSIG:w[0-9]+]], {{s[0-9]+}}
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; CHECK: fcvtzs [[SIG:w[0-9]+]], {{s[0-9]+}}
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; CHECK-DAG: fcvtzu [[UNSIG:w[0-9]+]], {{s[0-9]+}}
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; CHECK-DAG: fcvtzs [[SIG:w[0-9]+]], {{s[0-9]+}}
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%res = sub i32 %signed, %unsigned
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; CHECK: sub {{w[0-9]+}}, [[SIG]], [[UNSIG]]
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@ -20,8 +20,8 @@ define i32 @test_doubletoi32(double %in) {
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%signed = fptosi double %in to i32
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%unsigned = fptoui double %in to i32
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; CHECK: fcvtzu [[UNSIG:w[0-9]+]], {{d[0-9]+}}
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; CHECK: fcvtzs [[SIG:w[0-9]+]], {{d[0-9]+}}
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; CHECK-DAG: fcvtzu [[UNSIG:w[0-9]+]], {{d[0-9]+}}
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; CHECK-DAG: fcvtzs [[SIG:w[0-9]+]], {{d[0-9]+}}
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%res = sub i32 %signed, %unsigned
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; CHECK: sub {{w[0-9]+}}, [[SIG]], [[UNSIG]]
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@ -35,8 +35,8 @@ define i64 @test_floattoi64(float %in) {
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%signed = fptosi float %in to i64
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%unsigned = fptoui float %in to i64
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; CHECK: fcvtzu [[UNSIG:x[0-9]+]], {{s[0-9]+}}
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; CHECK: fcvtzs [[SIG:x[0-9]+]], {{s[0-9]+}}
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; CHECK-DAG: fcvtzu [[UNSIG:x[0-9]+]], {{s[0-9]+}}
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; CHECK-DAG: fcvtzs [[SIG:x[0-9]+]], {{s[0-9]+}}
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%res = sub i64 %signed, %unsigned
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; CHECK: sub {{x[0-9]+}}, [[SIG]], [[UNSIG]]
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@ -50,8 +50,8 @@ define i64 @test_doubletoi64(double %in) {
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%signed = fptosi double %in to i64
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%unsigned = fptoui double %in to i64
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; CHECK: fcvtzu [[UNSIG:x[0-9]+]], {{d[0-9]+}}
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; CHECK: fcvtzs [[SIG:x[0-9]+]], {{d[0-9]+}}
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; CHECK-DAG: fcvtzu [[UNSIG:x[0-9]+]], {{d[0-9]+}}
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; CHECK-DAG: fcvtzs [[SIG:x[0-9]+]], {{d[0-9]+}}
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%res = sub i64 %signed, %unsigned
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; CHECK: sub {{x[0-9]+}}, [[SIG]], [[UNSIG]]
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@ -65,8 +65,8 @@ define float @test_i32tofloat(i32 %in) {
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%signed = sitofp i32 %in to float
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%unsigned = uitofp i32 %in to float
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; CHECK: ucvtf [[UNSIG:s[0-9]+]], {{w[0-9]+}}
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; CHECK: scvtf [[SIG:s[0-9]+]], {{w[0-9]+}}
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; CHECK-DAG: ucvtf [[UNSIG:s[0-9]+]], {{w[0-9]+}}
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; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{w[0-9]+}}
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%res = fsub float %signed, %unsigned
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; CHECL: fsub {{s[0-9]+}}, [[SIG]], [[UNSIG]]
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@ -79,8 +79,8 @@ define double @test_i32todouble(i32 %in) {
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%signed = sitofp i32 %in to double
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%unsigned = uitofp i32 %in to double
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; CHECK: ucvtf [[UNSIG:d[0-9]+]], {{w[0-9]+}}
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; CHECK: scvtf [[SIG:d[0-9]+]], {{w[0-9]+}}
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; CHECK-DAG: ucvtf [[UNSIG:d[0-9]+]], {{w[0-9]+}}
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; CHECK-DAG: scvtf [[SIG:d[0-9]+]], {{w[0-9]+}}
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%res = fsub double %signed, %unsigned
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; CHECK: fsub {{d[0-9]+}}, [[SIG]], [[UNSIG]]
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@ -93,8 +93,8 @@ define float @test_i64tofloat(i64 %in) {
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%signed = sitofp i64 %in to float
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%unsigned = uitofp i64 %in to float
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; CHECK: ucvtf [[UNSIG:s[0-9]+]], {{x[0-9]+}}
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; CHECK: scvtf [[SIG:s[0-9]+]], {{x[0-9]+}}
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; CHECK-DAG: ucvtf [[UNSIG:s[0-9]+]], {{x[0-9]+}}
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; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{x[0-9]+}}
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%res = fsub float %signed, %unsigned
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; CHECK: fsub {{s[0-9]+}}, [[SIG]], [[UNSIG]]
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@ -107,8 +107,8 @@ define double @test_i64todouble(i64 %in) {
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%signed = sitofp i64 %in to double
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%unsigned = uitofp i64 %in to double
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; CHECK: ucvtf [[UNSIG:d[0-9]+]], {{x[0-9]+}}
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; CHECK: scvtf [[SIG:d[0-9]+]], {{x[0-9]+}}
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; CHECK-DAG: ucvtf [[UNSIG:d[0-9]+]], {{x[0-9]+}}
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; CHECK-DAG: scvtf [[SIG:d[0-9]+]], {{x[0-9]+}}
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%res = fsub double %signed, %unsigned
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; CHECK: sub {{d[0-9]+}}, [[SIG]], [[UNSIG]]
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@ -129,8 +129,9 @@ define float @test_fnmsub_unfused(float %a, float %b, float %c) {
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%diff = fsub float %nega, %prod
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; CHECK: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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; CHECK-NOFAST-NOT: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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; CHECK-NOFAST: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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; CHECK-NOFAST: fneg {{s[0-9]+}}, {{s[0-9]+}}
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; CHECK-NOFAST: fsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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; CHECK-NOFAST-DAG: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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; CHECK-NOFAST-DAG: fneg {{s[0-9]+}}, {{s[0-9]+}}
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; CHECK-NOFAST-DAG: fsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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; CHECK-NOFAST: ret
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ret float %diff
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}
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@ -150,14 +150,14 @@ define i1 @test_setcc2() {
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; Technically, everything after the call to __letf2 is redundant, but we'll let
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; LLVM have its fun for now.
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%val = fcmp ugt fp128 %lhs, %rhs
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; CHECK: bl __unordtf2
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; CHECK: mov x[[UNORDERED:[0-9]+]], x0
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; CHECK: bl __gttf2
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; CHECK: cmp w0, #0
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; CHECK: csinc [[GT:w[0-9]+]], wzr, wzr, le
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; CHECK: cmp w[[UNORDERED]], #0
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; CHECK: bl __unordtf2
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; CHECK: cmp w0, #0
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; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq
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; CHECK: orr w0, [[UNORDERED]], [[GT]]
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ret i1 %val
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@ -174,15 +174,14 @@ define i32 @test_br_cc() {
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; olt == !uge, which LLVM unfortunately "optimizes" this to.
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%cond = fcmp olt fp128 %lhs, %rhs
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; CHECK: bl __unordtf2
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; CHECK: mov x[[UNORDERED:[0-9]+]], x0
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; CHECK: bl __getf2
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; CHECK: cmp w0, #0
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; CHECK: csinc [[OGE:w[0-9]+]], wzr, wzr, lt
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; CHECK: cmp w[[UNORDERED]], #0
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; CHECK: bl __unordtf2
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; CHECK: cmp w0, #0
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; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq
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; CHECK: orr [[UGE:w[0-9]+]], [[UNORDERED]], [[OGE]]
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; CHECK: cbnz [[UGE]], [[RET29:.LBB[0-9]+_[0-9]+]]
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br i1 %cond, label %iftrue, label %iffalse
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@ -9,12 +9,13 @@ define void @check_float() {
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%val = load float* @varf32
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%newval1 = fadd float %val, 8.5
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store volatile float %newval1, float* @varf32
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; CHECK: fmov {{s[0-9]+}}, #8.5
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; CHECK-DAG: fmov [[EIGHT5:s[0-9]+]], #8.5
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%newval2 = fadd float %val, 128.0
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store volatile float %newval2, float* @varf32
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; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI0_0
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; CHECK-DAG: ldr [[HARD:s[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI0_0
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; CHECK: ret
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ret void
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}
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@ -24,11 +25,12 @@ define void @check_double() {
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%val = load double* @varf64
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%newval1 = fadd double %val, 8.5
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store volatile double %newval1, double* @varf64
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; CHECK: fmov {{d[0-9]+}}, #8.5
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; CHECK-DAG: fmov {{d[0-9]+}}, #8.5
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%newval2 = fadd double %val, 128.0
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store volatile double %newval2, double* @varf64
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; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI1_0
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; CHECK-DAG: ldr {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI1_0
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; CHECK: ret
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ret void
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}
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@ -35,15 +35,15 @@ define void @take_struct(%myStruct* byval %structval) {
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%addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
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%addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
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%val0 = load i32* %addr0
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%val0 = load volatile i32* %addr0
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; Some weird move means x0 is used for one access
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; CHECK: ldr [[REG32:w[0-9]+]], [{{x[0-9]+|sp}}, #12]
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store i32 %val0, i32* @var32
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store volatile i32 %val0, i32* @var32
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; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32]
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%val1 = load i64* %addr1
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%val1 = load volatile i64* %addr1
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; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}]
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store i64 %val1, i64* @var64
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store volatile i64 %val1, i64* @var64
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; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
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ret void
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@ -56,14 +56,14 @@ define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %st
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%addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
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%addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
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%val0 = load i32* %addr0
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%val0 = load volatile i32* %addr0
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; Some weird move means x0 is used for one access
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; CHECK: add x[[STRUCTVAL_ADDR:[0-9]+]], sp, #16
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; CHECK: ldr [[REG32:w[0-9]+]], [x[[STRUCTVAL_ADDR]], #12]
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store i32 %val0, i32* @var32
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; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32]
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%val1 = load i64* %addr1
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%val1 = load volatile i64* %addr1
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; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16]
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store i64 %val1, i64* @var64
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; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
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@ -130,17 +130,17 @@ define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var
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double %notstacked) {
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; CHECK-LABEL: struct_on_stack:
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%addr = getelementptr %myStruct* %struct, i64 0, i32 0
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%val64 = load i64* %addr
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store i64 %val64, i64* @var64
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%val64 = load volatile i64* %addr
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store volatile i64 %val64, i64* @var64
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; Currently nothing on local stack, so struct should be at sp
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; CHECK: ldr [[VAL64:x[0-9]+]], [sp]
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; CHECK: str [[VAL64]], [{{x[0-9]+}}, #:lo12:var64]
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store double %notstacked, double* @vardouble
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store volatile double %notstacked, double* @vardouble
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; CHECK-NOT: ldr d0
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; CHECK: str d0, [{{x[0-9]+}}, #:lo12:vardouble
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%retval = load i32* %stacked
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%retval = load volatile i32* %stacked
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ret i32 %retval
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; CHECK: ldr w0, [sp, #16]
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}
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@ -176,10 +176,10 @@ define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
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; CHECK: check_i128_stackalign
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store i128 %stack2, i128* @var128
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; Nothing local on stack in current codegen, so first stack is 16 away
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; CHECK: ldr {{x[0-9]+}}, [sp, #16]
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; CHECK: add x[[REG:[0-9]+]], sp, #16
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; CHECK: ldr {{x[0-9]+}}, [x[[REG]], #8]
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; Important point is that we address sp+24 for second dword
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; CHECK: add [[REG:x[0-9]+]], sp, #16
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; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG]], #8]
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; CHECK: ldr {{x[0-9]+}}, [sp, #16]
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ret void
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}
|
||||
|
||||
|
@ -21,15 +21,15 @@ define void @simple_args() {
|
||||
%char1 = load i8* @var8
|
||||
%char2 = load i8* @var8_2
|
||||
call void @take_i8s(i8 %char1, i8 %char2)
|
||||
; CHECK: ldrb w0, [{{x[0-9]+}}, #:lo12:var8]
|
||||
; CHECK: ldrb w1, [{{x[0-9]+}}, #:lo12:var8_2]
|
||||
; CHECK-DAG: ldrb w0, [{{x[0-9]+}}, #:lo12:var8]
|
||||
; CHECK-DAG: ldrb w1, [{{x[0-9]+}}, #:lo12:var8_2]
|
||||
; CHECK: bl take_i8s
|
||||
|
||||
%float1 = load float* @varfloat
|
||||
%float2 = load float* @varfloat_2
|
||||
call void @take_floats(float %float1, float %float2)
|
||||
; CHECK: ldr s1, [{{x[0-9]+}}, #:lo12:varfloat_2]
|
||||
; CHECK: ldr s0, [{{x[0-9]+}}, #:lo12:varfloat]
|
||||
; CHECK-DAG: ldr s1, [{{x[0-9]+}}, #:lo12:varfloat_2]
|
||||
; CHECK-DAG: ldr s0, [{{x[0-9]+}}, #:lo12:varfloat]
|
||||
; CHECK: bl take_floats
|
||||
|
||||
ret void
|
||||
@ -75,16 +75,17 @@ declare void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
|
||||
float %var8)
|
||||
|
||||
define void @check_stack_args() {
|
||||
; CHECK-LABEL: check_stack_args:
|
||||
call i32 @struct_on_stack(i8 0, i16 12, i32 42, i64 99, i128 1,
|
||||
i32* @var32, %myStruct* byval @varstruct,
|
||||
i32 999, double 1.0)
|
||||
; Want to check that the final double is passed in registers and
|
||||
; that varstruct is passed on the stack. Rather dependent on how a
|
||||
; memcpy gets created, but the following works for now.
|
||||
; CHECK: mov x0, sp
|
||||
; CHECK: str {{w[0-9]+}}, [x0]
|
||||
; CHECK: str {{w[0-9]+}}, [x0, #12]
|
||||
; CHECK: fmov d0,
|
||||
; CHECK: mov x[[SPREG:[0-9]+]], sp
|
||||
; CHECK-DAG: str {{w[0-9]+}}, [x[[SPREG]]]
|
||||
; CHECK-DAG: str {{w[0-9]+}}, [x[[SPREG]], #12]
|
||||
; CHECK-DAG: fmov d0,
|
||||
; CHECK: bl struct_on_stack
|
||||
|
||||
call void @stacked_fpu(float -1.0, double 1.0, float 4.0, float 2.0,
|
||||
|
@ -65,8 +65,7 @@ define void @floating_lits() {
|
||||
%floatval = load float* @varfloat
|
||||
%newfloat = fadd float %floatval, 128.0
|
||||
; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI1_[0-9]+]]
|
||||
; CHECK: ldr {{s[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]]
|
||||
; CHECK: fadd
|
||||
; CHECK: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]], #:lo12:[[CURLIT]]]
|
||||
|
||||
; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI1_[0-9]+]]
|
||||
; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
|
||||
@ -80,8 +79,9 @@ define void @floating_lits() {
|
||||
%doubleval = load double* @vardouble
|
||||
%newdouble = fadd double %doubleval, 129.0
|
||||
; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI1_[0-9]+]]
|
||||
; CHECK: ldr {{d[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]]
|
||||
; CHECK: fadd
|
||||
; CHECK: ldr [[LIT129:d[0-9]+]], [x[[LITBASE]], #:lo12:[[CURLIT]]]
|
||||
; CHECK: fadd {{s[0-9]+}}, {{s[0-9]+}}, [[LIT128]]
|
||||
; CHECK: fadd {{d[0-9]+}}, {{d[0-9]+}}, [[LIT129]]
|
||||
|
||||
; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI1_[0-9]+]]
|
||||
; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
|
||||
|
@ -10,8 +10,8 @@ define i32 @test_generaldynamic() {
|
||||
ret i32 %val
|
||||
|
||||
; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var
|
||||
; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var
|
||||
; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var]
|
||||
; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var
|
||||
; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var]
|
||||
; CHECK: .tlsdesccall general_dynamic_var
|
||||
; CHECK-NEXT: blr [[CALLEE]]
|
||||
|
||||
@ -19,8 +19,8 @@ define i32 @test_generaldynamic() {
|
||||
; CHECK: ldr w0, [x[[TP]], x0]
|
||||
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
|
||||
|
||||
}
|
||||
@ -31,8 +31,8 @@ define i32* @test_generaldynamic_addr() {
|
||||
ret i32* @general_dynamic_var
|
||||
|
||||
; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var
|
||||
; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var
|
||||
; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var]
|
||||
; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var
|
||||
; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var]
|
||||
; CHECK: .tlsdesccall general_dynamic_var
|
||||
; CHECK-NEXT: blr [[CALLEE]]
|
||||
|
||||
@ -40,8 +40,8 @@ define i32* @test_generaldynamic_addr() {
|
||||
; CHECK: add x0, [[TP]], x0
|
||||
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
|
||||
|
||||
}
|
||||
@ -55,8 +55,8 @@ define i32 @test_localdynamic() {
|
||||
ret i32 %val
|
||||
|
||||
; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
|
||||
; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_
|
||||
; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_]
|
||||
; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_
|
||||
; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_]
|
||||
; CHECK: .tlsdesccall _TLS_MODULE_BASE_
|
||||
; CHECK-NEXT: blr [[CALLEE]]
|
||||
|
||||
@ -66,8 +66,8 @@ define i32 @test_localdynamic() {
|
||||
; CHECK: ldr w0, [x0, [[DTP_OFFSET]]]
|
||||
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
|
||||
|
||||
}
|
||||
@ -78,8 +78,8 @@ define i32* @test_localdynamic_addr() {
|
||||
ret i32* @local_dynamic_var
|
||||
|
||||
; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
|
||||
; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_
|
||||
; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_]
|
||||
; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_
|
||||
; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_]
|
||||
; CHECK: .tlsdesccall _TLS_MODULE_BASE_
|
||||
; CHECK-NEXT: blr [[CALLEE]]
|
||||
|
||||
@ -89,8 +89,8 @@ define i32* @test_localdynamic_addr() {
|
||||
; CHECK: add x0, x0, [[DTP_OFFSET]]
|
||||
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
|
||||
|
||||
}
|
||||
@ -110,8 +110,8 @@ define i32 @test_localdynamic_deduplicate() {
|
||||
ret i32 %sum
|
||||
|
||||
; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
|
||||
; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_
|
||||
; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_]
|
||||
; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_
|
||||
; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_]
|
||||
; CHECK: .tlsdesccall _TLS_MODULE_BASE_
|
||||
; CHECK-NEXT: blr [[CALLEE]]
|
||||
|
||||
|
@ -9,6 +9,7 @@ declare void @llvm.va_start(i8*)
|
||||
define void @test_simple(i32 %n, ...) {
|
||||
; CHECK-LABEL: test_simple:
|
||||
; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
|
||||
; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
|
||||
; CHECK: mov x[[FPRBASE:[0-9]+]], sp
|
||||
; CHECK: str q7, [x[[FPRBASE]], #112]
|
||||
; CHECK: add x[[GPRBASE:[0-9]+]], sp, #[[GPRFROMSP:[0-9]+]]
|
||||
@ -21,7 +22,6 @@ define void @test_simple(i32 %n, ...) {
|
||||
|
||||
%addr = bitcast %va_list* @var to i8*
|
||||
call void @llvm.va_start(i8* %addr)
|
||||
; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
|
||||
; CHECK: movn [[VR_OFFS:w[0-9]+]], #127
|
||||
; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28]
|
||||
; CHECK: movn [[GR_OFFS:w[0-9]+]], #55
|
||||
@ -131,12 +131,13 @@ define void @test_va_copy() {
|
||||
; Check beginning and end again:
|
||||
|
||||
; CHECK: ldr [[BLOCK:x[0-9]+]], [{{x[0-9]+}}, #:lo12:var]
|
||||
; CHECK: str [[BLOCK]], [{{x[0-9]+}}, #:lo12:second_list]
|
||||
|
||||
; CHECK: add x[[DEST_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:second_list
|
||||
; CHECK: add x[[SRC_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
|
||||
|
||||
; CHECK: str [[BLOCK]], [{{x[0-9]+}}, #:lo12:second_list]
|
||||
|
||||
; CHECK: ldr [[BLOCK:x[0-9]+]], [x[[SRC_LIST]], #24]
|
||||
; CHECK: add x[[DEST_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:second_list
|
||||
|
||||
; CHECK: str [[BLOCK]], [x[[DEST_LIST]], #24]
|
||||
|
||||
ret void
|
||||
|
Loading…
Reference in New Issue
Block a user