mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met:
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.
e.g.
vldr.32 s0, [r1]
vldr.32 s1, [r0]
vcmpe.f32 s1, s0
vmrs apsr_nzcv, fpscr
beq LBB0_2
=>
ldr r1, [r1]
ldr r0, [r0]
cmp r0, r1
beq LBB0_2
More complicated cases will be implemented in subsequent patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107852 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
7835f1fcdb
commit
515fe3a588
@ -59,7 +59,7 @@ EnableARMTailCalls("arm-tail-calls", cl::Hidden,
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static cl::opt<bool>
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EnableARMLongCalls("arm-long-calls", cl::Hidden,
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cl::desc("Generate calls via indirect call instructions."),
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cl::desc("Generate calls via indirect call instructions"),
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cl::init(false));
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static cl::opt<bool>
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@ -69,7 +69,7 @@ ARMInterworking("arm-interworking", cl::Hidden,
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static cl::opt<bool>
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EnableARMCodePlacement("arm-code-placement", cl::Hidden,
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cl::desc("Enable code placement pass for ARM."),
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cl::desc("Enable code placement pass for ARM"),
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cl::init(false));
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static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
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@ -2273,9 +2273,42 @@ ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
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}
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static bool canBitcastToInt(SDNode *Op) {
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return Op->hasOneUse() &&
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ISD::isNormalLoad(Op) &&
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Op->getValueType(0) == MVT::f32;
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}
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static SDValue bitcastToInt(SDValue Op, SelectionDAG &DAG) {
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if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
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return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
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Ld->getChain(), Ld->getBasePtr(),
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Ld->getSrcValue(), Ld->getSrcValueOffset(),
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Ld->isVolatile(), Ld->isNonTemporal(),
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Ld->getAlignment());
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llvm_unreachable("Unknown VFP cmp argument!");
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}
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/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
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static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
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DebugLoc dl) {
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SDValue
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ARMTargetLowering::getVFPCmp(SDValue &LHS, SDValue &RHS, ISD::CondCode CC,
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SDValue &ARMCC, SelectionDAG &DAG,
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DebugLoc dl) const {
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if ((CC == ISD::SETEQ || CC == ISD::SETOEQ ||
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CC == ISD::SETNE || CC == ISD::SETUNE) &&
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canBitcastToInt(LHS.getNode()) && canBitcastToInt(RHS.getNode())) {
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// If there are no othter uses of the CMP operands, and the condition
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// code is EQ oe NE, we can optimize it to an integer comparison.
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if (CC == ISD::SETOEQ)
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CC = ISD::SETEQ;
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else if (CC == ISD::SETUNE)
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CC = ISD::SETNE;
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LHS = bitcastToInt(LHS, DAG);
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RHS = bitcastToInt(RHS, DAG);
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return getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
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}
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SDValue Cmp;
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if (!isFloatingPointZero(RHS))
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Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
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@ -2305,13 +2338,13 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
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SDValue Cmp = getVFPCmp(LHS, RHS, CC, ARMCC, DAG, dl);
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SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
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ARMCC, CCR, Cmp);
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ARMCC, CCR, Cmp);
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if (CondCode2 != ARMCC::AL) {
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SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
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// FIXME: Needs another CMP because flag can have but one use.
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SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
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SDValue Cmp2 = getVFPCmp(LHS, RHS, CC, ARMCC2, DAG, dl);
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Result = DAG.getNode(ARMISD::CMOV, dl, VT,
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Result, TrueVal, ARMCC2, CCR, Cmp2);
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}
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@ -2338,8 +2371,8 @@ SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
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ARMCC::CondCodes CondCode, CondCode2;
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FPCCToARMCC(CC, CondCode, CondCode2);
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SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
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SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
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SDValue Cmp = getVFPCmp(LHS, RHS, CC, ARMCC, DAG, dl);
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
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SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
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@ -2427,7 +2460,7 @@ static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(Opc, dl, VT, Op);
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}
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static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
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SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
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// Implement fcopysign with a fabs and a conditional fneg.
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SDValue Tmp0 = Op.getOperand(0);
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SDValue Tmp1 = Op.getOperand(1);
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@ -2435,8 +2468,10 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
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EVT VT = Op.getValueType();
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EVT SrcVT = Tmp1.getValueType();
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SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
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SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
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SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
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SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
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SDValue Cmp = getVFPCmp(Tmp1, FP0,
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ISD::SETLT, ARMCC, DAG, dl);
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
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}
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@ -313,6 +313,7 @@ namespace llvm {
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SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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@ -363,6 +364,8 @@ namespace llvm {
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SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) const;
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SDValue getVFPCmp(SDValue &LHS, SDValue &RHS, ISD::CondCode CC,
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SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) const;
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MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
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MachineBasicBlock *BB,
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29
test/CodeGen/ARM/fpcmp-opt.ll
Normal file
29
test/CodeGen/ARM/fpcmp-opt.ll
Normal file
@ -0,0 +1,29 @@
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; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
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; rdar://7461510
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define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
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entry:
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; CHECK: t1:
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; CHECK-NOT: vldr
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; CHECK: ldr
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; CHECK: ldr
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; CHECK: cmp r0, r1
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; CHECK-NOT: vcmpe.f32
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; CHECK-NOT: vmrs
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; CHECK: beq
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%0 = load float* %a
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%1 = load float* %b
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%2 = fcmp une float %0, %1
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br i1 %2, label %bb1, label %bb2
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bb1:
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%3 = call i32 @bar()
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ret i32 %3
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bb2:
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%4 = call i32 @foo()
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ret i32 %4
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}
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declare i32 @bar()
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declare i32 @foo()
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