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To handle s* registers in emitVFPLoadStoreMultipleInstruction().

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Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104652 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Shih-wei Liao
2010-05-26 00:02:28 +00:00
parent 96ac5156ca
commit 5170b71143
1 changed files with 12 additions and 7 deletions
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5
lib/Target/ARM/ARMCodeEmitter.cpp
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@@ -1459,7 +1459,12 @@ ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
break;
++NumRegs;
}
// Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
// Otherwise, it will be 0, in the case of 32-bit registers.
if(Binary & 0x100)
Binary |= NumRegs * 2;
else
Binary |= NumRegs;
emitWordLE(Binary);
}