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Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143682 91177308-0d34-0410-b5e6-96231b3b80d8
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test/CodeGen/X86/f16c-intrinsics.ll
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32
test/CodeGen/X86/f16c-intrinsics.ll
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; RUN: llc < %s -march=x86 -mattr=+avx,+f16c | FileCheck %s
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define <4 x float> @test_x86_vcvtph2ps_128(<8 x i16> %a0) {
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; CHECK: vcvtph2ps
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%res = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>) nounwind readonly
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define <8 x float> @test_x86_vcvtph2ps_256(<8 x i16> %a0) {
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; CHECK: vcvtph2ps
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%res = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %a0) ; <<8 x float>> [#uses=1]
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ret <8 x float> %res
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}
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declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) nounwind readonly
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define <8 x i16> @test_x86_vcvtps2ph_128(<4 x float> %a0) {
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; CHECK: vcvtps2ph
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%res = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float>, i32) nounwind readonly
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define <8 x i16> @test_x86_vcvtps2ph_256(<8 x float> %a0) {
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; CHECK: vcvtps2ph
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%res = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readonly
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