mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-29 13:54:57 +00:00
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
47245422a4
commit
52925b60f1
@ -741,10 +741,16 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
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.Case("al", ARMCC::AL)
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.Default(~0U);
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if (CC != ~0U)
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Head = Head.slice(0, Head.size() - 2);
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else
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if (CC != ~0U) {
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if (CC == ARMCC::LS &&
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(Head.compare("vmls") == 0 || Head.compare("vnmls") == 0)) {
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CC = ARMCC::AL;
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} else {
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Head = Head.slice(0, Head.size() - 2);
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}
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} else {
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CC = ARMCC::AL;
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}
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Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
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Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
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@ -1,434 +0,0 @@
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; RUN: llc -mtriple=armv7-apple-darwin -mcpu=cortex-a8 -mattr=-neonfp -show-mc-encoding < %s | FileCheck %s
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; XFAIL: *
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; FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
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; should run on .s source files rather than using llc to generate the
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; assembly.
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define double @f1(double %a, double %b) nounwind readnone {
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entry:
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; CHECK: f1
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; CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
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%add = fadd double %a, %b
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ret double %add
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}
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define float @f2(float %a, float %b) nounwind readnone {
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entry:
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; CHECK: f2
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; CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
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%add = fadd float %a, %b
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ret float %add
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}
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define double @f3(double %a, double %b) nounwind readnone {
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entry:
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; CHECK: f3
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; CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
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%sub = fsub double %a, %b
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ret double %sub
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}
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define float @f4(float %a, float %b) nounwind readnone {
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entry:
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; CHECK: f4
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; CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
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%sub = fsub float %a, %b
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ret float %sub
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}
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define double @f5(double %a, double %b) nounwind readnone {
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entry:
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; CHECK: f5
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; CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
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%div = fdiv double %a, %b
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ret double %div
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}
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define float @f6(float %a, float %b) nounwind readnone {
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entry:
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; CHECK: f6
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; CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
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%div = fdiv float %a, %b
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ret float %div
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}
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define double @f7(double %a, double %b) nounwind readnone {
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entry:
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; CHECK: f7
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; CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
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%mul = fmul double %a, %b
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ret double %mul
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}
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define float @f8(float %a, float %b) nounwind readnone {
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entry:
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; CHECK: f8
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; CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
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%mul = fmul float %a, %b
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ret float %mul
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}
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define double @f9(double %a, double %b) nounwind readnone {
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entry:
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; CHECK: f9
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; CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
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%mul = fmul double %a, %b
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%sub = fsub double -0.000000e+00, %mul
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ret double %sub
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}
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define void @f10(float %a, float %b, float* %c) nounwind readnone {
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entry:
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; CHECK: f10
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; CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
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%mul = fmul float %a, %b
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%sub = fsub float -0.000000e+00, %mul
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store float %sub, float* %c, align 4
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ret void
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}
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define i1 @f11(double %a, double %b) nounwind readnone {
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entry:
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; CHECK: f11
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; CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee]
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%cmp = fcmp oeq double %a, %b
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ret i1 %cmp
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}
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define i1 @f12(float %a, float %b) nounwind readnone {
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entry:
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; CHECK: f12
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; CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee]
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%cmp = fcmp oeq float %a, %b
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ret i1 %cmp
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}
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define i1 @f13(double %a) nounwind readnone {
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entry:
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; CHECK: f13
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; CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee]
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%cmp = fcmp oeq double %a, 0.000000e+00
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ret i1 %cmp
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}
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define i1 @f14(float %a) nounwind readnone {
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entry:
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; CHECK: f14
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; CHECK: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee]
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%cmp = fcmp oeq float %a, 0.000000e+00
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ret i1 %cmp
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}
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define double @f15(double %a) nounwind {
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entry:
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; CHECK: f15
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; CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee]
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%call = tail call double @fabsl(double %a)
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ret double %call
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}
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declare double @fabsl(double)
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define float @f16(float %a) nounwind {
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entry:
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; CHECK: f16
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; FIXME: This call generates a "bfc" instruction instead of "vabs.f32".
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%call = tail call float @fabsf(float %a)
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ret float %call
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}
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declare float @fabsf(float)
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define float @f17(double %a) nounwind readnone {
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entry:
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; CHECK: f17
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; CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
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%conv = fptrunc double %a to float
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ret float %conv
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}
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define double @f18(float %a) nounwind readnone {
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entry:
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; CHECK: f18
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; CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee]
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%conv = fpext float %a to double
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ret double %conv
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}
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define double @f19(double %a) nounwind readnone {
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entry:
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; CHECK: f19
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; CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee]
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%sub = fsub double -0.000000e+00, %a
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ret double %sub
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}
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define float @f20(float %a) nounwind readnone {
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entry:
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; CHECK: f20
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; FIXME: This produces an 'eor' instruction.
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%sub = fsub float -0.000000e+00, %a
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ret float %sub
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}
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define double @f21(double %a) nounwind readnone {
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entry:
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; CHECK: f21
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; CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee]
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%call = tail call double @sqrtl(double %a) nounwind
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ret double %call
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}
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declare double @sqrtl(double) readnone
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define float @f22(float %a) nounwind readnone {
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entry:
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; CHECK: f22
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; CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee]
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%call = tail call float @sqrtf(float %a) nounwind
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ret float %call
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}
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declare float @sqrtf(float) readnone
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define double @f23(i32 %a) nounwind readnone {
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entry:
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; CHECK: f23
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; CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee]
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%conv = sitofp i32 %a to double
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ret double %conv
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}
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define float @f24(i32 %a) nounwind readnone {
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entry:
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; CHECK: f24
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; CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee]
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%conv = sitofp i32 %a to float
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ret float %conv
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}
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define double @f25(i32 %a) nounwind readnone {
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entry:
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; CHECK: f25
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; CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee]
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%conv = uitofp i32 %a to double
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ret double %conv
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}
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define float @f26(i32 %a) nounwind readnone {
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entry:
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; CHECK: f26
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; CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee]
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%conv = uitofp i32 %a to float
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ret float %conv
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}
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define i32 @f27(double %a) nounwind readnone {
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entry:
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; CHECK: f27
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; CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee]
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%conv = fptosi double %a to i32
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ret i32 %conv
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}
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define i32 @f28(float %a) nounwind readnone {
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entry:
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; CHECK: f28
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; CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee]
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%conv = fptosi float %a to i32
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ret i32 %conv
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}
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define i32 @f29(double %a) nounwind readnone {
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entry:
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; CHECK: f29
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; CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee]
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%conv = fptoui double %a to i32
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ret i32 %conv
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}
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define i32 @f30(float %a) nounwind readnone {
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entry:
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; CHECK: f30
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; CHECK: vcvt.u32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbc,0xee]
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%conv = fptoui float %a to i32
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ret i32 %conv
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}
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define double @f90(double %a, double %b, double %c) nounwind readnone {
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entry:
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; CHECK: f90
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; FIXME: vmla.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x42,0xee]
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%mul = fmul double %a, %b
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%add = fadd double %mul, %c
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ret double %add
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}
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define float @f91(float %a, float %b, float %c) nounwind readnone {
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entry:
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; CHECK: f91
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; CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee]
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%mul = fmul float %a, %b
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%add = fadd float %mul, %c
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ret float %add
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}
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define double @f92(double %a, double %b, double %c) nounwind readnone {
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entry:
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; CHECK: f92
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; CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee]
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%mul = fmul double %a, %b
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%sub = fsub double %c, %mul
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ret double %sub
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}
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define float @f93(float %a, float %b, float %c) nounwind readnone {
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entry:
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; CHECK: f93
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; CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee]
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%mul = fmul float %a, %b
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%sub = fsub float %c, %mul
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ret float %sub
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}
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define double @f94(double %a, double %b, double %c) nounwind readnone {
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entry:
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; CHECK: f94
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; CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee]
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%mul = fmul double %a, %b
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%sub = fsub double -0.000000e+00, %mul
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%sub3 = fsub double %sub, %c
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ret double %sub3
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}
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define float @f95(float %a, float %b, float %c) nounwind readnone {
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entry:
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; CHECK: f95
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; CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee]
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%mul = fmul float %a, %b
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%sub = fsub float -0.000000e+00, %mul
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%sub3 = fsub float %sub, %c
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ret float %sub3
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}
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define double @f96(double %a, double %b, double %c) nounwind readnone {
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entry:
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; CHECK: f96
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; CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee]
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%mul = fmul double %a, %b
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%sub = fsub double %mul, %c
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ret double %sub
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}
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define float @f97(float %a, float %b, float %c) nounwind readnone {
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entry:
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; CHECK: f97
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; CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee]
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%mul = fmul float %a, %b
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%sub = fsub float %mul, %c
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ret float %sub
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}
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; FIXME: Check for fmstat instruction.
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define double @f98(double %a, i32 %i) nounwind readnone {
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entry:
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%cmp = icmp eq i32 %i, 3
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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; CHECK: f98
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; CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e]
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%sub = fsub double -0.000000e+00, %a
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ret double %sub
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return: ; preds = %entry
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ret double %a
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}
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define float @f99(float %a, float %b, i32 %i) nounwind readnone {
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entry:
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%cmp = icmp eq i32 %i, 3
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br i1 %cmp, label %if.end, label %return
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if.end: ; preds = %entry
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; CHECK: f99
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; CHECK: vmovne s0, r0 @ encoding: [0x10,0x0a,0x00,0x1e]
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; CHECK: vmoveq s0, r1 @ encoding: [0x10,0x1a,0x00,0x0e]
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ret float %b
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return: ; preds = %entry
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ret float %a
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}
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define i32 @f100() nounwind readnone {
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entry:
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; CHECK: f100
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; CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee]
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%0 = tail call i32 @llvm.arm.get.fpscr()
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ret i32 %0
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}
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declare i32 @llvm.arm.get.fpscr() nounwind readnone
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define void @f101(i32 %a) nounwind {
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entry:
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; CHECK: f101
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; CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
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tail call void @llvm.arm.set.fpscr(i32 %a)
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ret void
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}
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declare void @llvm.arm.set.fpscr(i32) nounwind
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define double @f102() nounwind readnone {
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entry:
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; CHECK: f102
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; CHECK: vmov.f64 d16, #3.000000e+00 @ encoding: [0x08,0x0b,0xf0,0xee]
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ret double 3.000000e+00
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}
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define float @f103(float %a) nounwind readnone {
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entry:
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; CHECK: f103
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; CHECK: vmov.f32 s0, #3.000000e+00 @ encoding: [0x08,0x0a,0xb0,0xee]
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%add = fadd float %a, 3.000000e+00
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ret float %add
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}
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define void @f104(float %a, float %b, float %c, float %d, float %e, float %f) nounwind {
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entry:
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; CHECK: f104
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; CHECK: vmov s0, r0 @ encoding: [0x10,0x0a,0x00,0xee]
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; CHECK: vmov s1, r1 @ encoding: [0x90,0x1a,0x00,0xee]
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; CHECK: vmov s2, r2 @ encoding: [0x10,0x2a,0x01,0xee]
|
||||
; CHECK: vmov s3, r3 @ encoding: [0x90,0x3a,0x01,0xee]
|
||||
%conv = fptosi float %a to i32
|
||||
%conv2 = fptosi float %b to i32
|
||||
%conv4 = fptosi float %c to i32
|
||||
%conv6 = fptosi float %d to i32
|
||||
%conv8 = fptosi float %e to i32
|
||||
%conv10 = fptosi float %f to i32
|
||||
tail call void @g104(i32 %conv, i32 %conv2, i32 %conv4, i32 %conv6, i32 %conv8, i32 %conv10) nounwind
|
||||
; CHECK: vmov r0, s0 @ encoding: [0x10,0x0a,0x10,0xee]
|
||||
; CHECK: vmov r1, s1 @ encoding: [0x90,0x1a,0x10,0xee]
|
||||
; CHECK: vmov r2, s2 @ encoding: [0x10,0x2a,0x11,0xee]
|
||||
; CHECK: vmov r3, s3 @ encoding: [0x90,0x3a,0x11,0xee]
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @g104(i32, i32, i32, i32, i32, i32)
|
||||
|
||||
define double @f105(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f105
|
||||
; CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec]
|
||||
%conv = uitofp i32 %a to double
|
||||
ret double %conv
|
||||
}
|
||||
160
test/MC/ARM/simple-fp-encoding.s
Normal file
160
test/MC/ARM/simple-fp-encoding.s
Normal file
@ -0,0 +1,160 @@
|
||||
// RUN: llvm-mc -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
|
||||
|
||||
// CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
|
||||
vadd.f64 d16, d17, d16
|
||||
|
||||
// CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
|
||||
vadd.f32 s0, s1, s0
|
||||
|
||||
// CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
|
||||
vsub.f64 d16, d17, d16
|
||||
|
||||
// CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
|
||||
vsub.f32 s0, s1, s0
|
||||
|
||||
// CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
|
||||
vdiv.f64 d16, d17, d16
|
||||
|
||||
// CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
|
||||
vdiv.f32 s0, s1, s0
|
||||
|
||||
// CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
|
||||
vmul.f64 d16, d17, d16
|
||||
|
||||
// CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
|
||||
vmul.f32 s0, s1, s0
|
||||
|
||||
// CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
|
||||
vnmul.f64 d16, d17, d16
|
||||
|
||||
// CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
|
||||
vnmul.f32 s0, s1, s0
|
||||
|
||||
// CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee]
|
||||
vcmpe.f64 d17, d16
|
||||
|
||||
// CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee]
|
||||
vcmpe.f32 s1, s0
|
||||
|
||||
// FIXME: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee]
|
||||
// vcmpe.f64 d16, #0
|
||||
|
||||
// FIXME: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee]
|
||||
// vcmpe.f32 s0, #0
|
||||
|
||||
// CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee]
|
||||
vabs.f64 d16, d16
|
||||
|
||||
// CHECK: vabs.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb0,0xee]
|
||||
vabs.f32 s0, s0
|
||||
|
||||
// CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
|
||||
vcvt.f32.f64 s0, d16
|
||||
|
||||
// CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee]
|
||||
vcvt.f64.f32 d16, s0
|
||||
|
||||
// CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee]
|
||||
vneg.f64 d16, d16
|
||||
|
||||
// CHECK: vneg.f32 s0, s0 @ encoding: [0x40,0x0a,0xb1,0xee]
|
||||
vneg.f32 s0, s0
|
||||
|
||||
// CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee]
|
||||
vsqrt.f64 d16, d16
|
||||
|
||||
// CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee]
|
||||
vsqrt.f32 s0, s0
|
||||
|
||||
// CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee]
|
||||
vcvt.f64.s32 d16, s0
|
||||
|
||||
// CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee]
|
||||
vcvt.f32.s32 s0, s0
|
||||
|
||||
// CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee]
|
||||
vcvt.f64.u32 d16, s0
|
||||
|
||||
// CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee]
|
||||
vcvt.f32.u32 s0, s0
|
||||
|
||||
// CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee]
|
||||
vcvt.s32.f64 s0, d16
|
||||
|
||||
// CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee]
|
||||
vcvt.s32.f32 s0, s0
|
||||
|
||||
// CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee]
|
||||
vcvt.u32.f64 s0, d16
|
||||
|
||||
// CHECK: vcvt.u32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbc,0xee]
|
||||
vcvt.u32.f32 s0, s0
|
||||
|
||||
// CHECK: vmla.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x42,0xee]
|
||||
vmla.f64 d16, d18, d17
|
||||
|
||||
// CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee]
|
||||
vmla.f32 s1, s2, s0
|
||||
|
||||
// CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee]
|
||||
vmls.f64 d16, d18, d17
|
||||
|
||||
// CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee]
|
||||
vmls.f32 s1, s2, s0
|
||||
|
||||
// CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee]
|
||||
vnmla.f64 d16, d18, d17
|
||||
|
||||
// CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee]
|
||||
vnmla.f32 s1, s2, s0
|
||||
|
||||
// CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee]
|
||||
vnmls.f64 d16, d18, d17
|
||||
|
||||
// CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee]
|
||||
vnmls.f32 s1, s2, s0
|
||||
|
||||
// FIXME: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
|
||||
// vmrs apsr_nzcv, fpscr
|
||||
|
||||
// CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e]
|
||||
vnegne.f64 d16, d16
|
||||
|
||||
// CHECK: vmovne s0, r0 @ encoding: [0x10,0x0a,0x00,0x1e]
|
||||
// CHECK: vmoveq s0, r1 @ encoding: [0x10,0x1a,0x00,0x0e]
|
||||
vmovne s0, r0
|
||||
vmoveq s0, r1
|
||||
|
||||
// CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee]
|
||||
vmrs r0, fpscr
|
||||
|
||||
// CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
|
||||
vmsr fpscr, r0
|
||||
|
||||
// FIXME: vmov.f64 d16, #3.000000e+00 @ encoding: [0x08,0x0b,0xf0,0xee]
|
||||
// vmov.f64 d16, #3.000000e+00
|
||||
|
||||
// FIXME: vmov.f32 s0, #3.000000e+00 @ encoding: [0x08,0x0a,0xb0,0xee]
|
||||
// vmov.f32 s0, #3.000000e+00
|
||||
|
||||
// CHECK: vmov s0, r0 @ encoding: [0x10,0x0a,0x00,0xee]
|
||||
// CHECK: vmov s1, r1 @ encoding: [0x90,0x1a,0x00,0xee]
|
||||
// CHECK: vmov s2, r2 @ encoding: [0x10,0x2a,0x01,0xee]
|
||||
// CHECK: vmov s3, r3 @ encoding: [0x90,0x3a,0x01,0xee]
|
||||
vmov s0, r0
|
||||
vmov s1, r1
|
||||
vmov s2, r2
|
||||
vmov s3, r3
|
||||
|
||||
// CHECK: vmov r0, s0 @ encoding: [0x10,0x0a,0x10,0xee]
|
||||
// CHECK: vmov r1, s1 @ encoding: [0x90,0x1a,0x10,0xee]
|
||||
// CHECK: vmov r2, s2 @ encoding: [0x10,0x2a,0x11,0xee]
|
||||
// CHECK: vmov r3, s3 @ encoding: [0x90,0x3a,0x11,0xee]
|
||||
vmov r0, s0
|
||||
vmov r1, s1
|
||||
vmov r2, s2
|
||||
vmov r3, s3
|
||||
|
||||
// CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec]
|
||||
vmov r0, r1, d16
|
||||
|
||||
Loading…
Reference in New Issue
Block a user