mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
CellSPU:
- Remove custom lowering for BRCOND - Add remaining functionality for branches in SPUInstrInfo, such as branch condition reversal and load/store folding. Updated BrCond test to reflect branch reversal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61597 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Scott Michel
parent
3d45f53b7a
commit
52d0001cfc
@ -147,10 +147,6 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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}
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}
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// Custom lower BRCOND for i8 to "promote" the result to whatever the result
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// operand happens to be:
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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// Expand the jumptable branches
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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@ -903,33 +899,6 @@ LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
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return SDValue();
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}
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static SDValue
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LowerBRCOND(SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) {
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SDValue Cond = Op.getOperand(1);
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MVT CondVT = Cond.getValueType();
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unsigned CondOpc;
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if (CondVT == MVT::i8) {
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SDValue CondOp0 = Cond.getOperand(0);
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if (Cond.getOpcode() == ISD::TRUNCATE) {
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// Use the truncate's value type and ANY_EXTEND the condition (DAGcombine
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// will then remove the truncate)
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CondVT = CondOp0.getValueType();
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CondOpc = ISD::ANY_EXTEND;
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} else {
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CondVT = MVT::i32; // default to something reasonable
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CondOpc = ISD::ZERO_EXTEND;
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}
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Cond = DAG.getNode(CondOpc, CondVT, Op.getOperand(1));
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return DAG.getNode(ISD::BRCOND, Op.getValueType(),
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Op.getOperand(0), Cond, Op.getOperand(2));
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}
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return SDValue(); // Unchanged
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}
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static SDValue
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LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
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{
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@ -2526,9 +2495,8 @@ static SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG)
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MVT Op0VT = Op0.getValueType();
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MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
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// Create shuffle mask
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if (Op0VT.getSimpleVT() == MVT::i128 && simpleVT == MVT::i64) {
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// least significant doubleword of quadword
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// Create shuffle mask, least significant doubleword of quadword
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unsigned maskHigh = 0x08090a0b;
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unsigned maskLow = 0x0c0d0e0f;
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// Use a shuffle to perform the truncation
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@ -2587,8 +2555,6 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
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return LowerConstant(Op, DAG);
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case ISD::ConstantFP:
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return LowerConstantFP(Op, DAG);
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case ISD::BRCOND:
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return LowerBRCOND(Op, DAG, *this);
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case ISD::FORMAL_ARGUMENTS:
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return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
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case ISD::CALL:
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@ -32,6 +32,7 @@ namespace {
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|| opc == SPU::BI);
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}
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//! Predicate for a conditional branch instruction
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inline bool isCondBranch(const MachineInstr *I) {
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unsigned opc = I->getOpcode();
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@ -50,9 +51,7 @@ SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
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: TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
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TM(tm),
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RI(*TM.getSubtargetImpl(), *this)
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{
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/* NOP */
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}
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{ /* NOP */ }
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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@ -135,7 +134,7 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isReg() &&
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MI.getOperand(1).isReg() &&
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"invalid SPU OR<type>_<vec> instruction!");
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"invalid SPU OR<type>_<vec> or LR instruction!");
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if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
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sourceReg = MI.getOperand(0).getReg();
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destReg = MI.getOperand(0).getReg();
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@ -146,6 +145,9 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
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case SPU::ORv16i8:
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case SPU::ORv8i16:
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case SPU::ORv4i32:
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case SPU::ORv2i64:
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case SPU::ORr8:
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case SPU::ORr16:
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case SPU::ORr32:
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case SPU::ORr64:
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case SPU::ORf32:
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@ -182,29 +184,12 @@ SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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case SPU::LQDr16: {
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const MachineOperand MOp1 = MI->getOperand(1);
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const MachineOperand MOp2 = MI->getOperand(2);
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if (MOp1.isImm()
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&& (MOp2.isFI()
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|| (MOp2.isReg() && MOp2.getReg() == SPU::R1))) {
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if (MOp2.isFI())
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FrameIndex = MOp2.getIndex();
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else
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FrameIndex = MOp1.getImm() / SPUFrameInfo::stackSlotSize();
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if (MOp1.isImm() && MOp2.isFI()) {
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FrameIndex = MOp2.getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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case SPU::LQXv4i32:
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case SPU::LQXr128:
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case SPU::LQXr64:
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case SPU::LQXr32:
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case SPU::LQXr16:
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if (MI->getOperand(1).isReg() && MI->getOperand(2).isReg()
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&& (MI->getOperand(2).getReg() == SPU::R1
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|| MI->getOperand(1).getReg() == SPU::R1)) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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@ -232,25 +217,6 @@ SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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}
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break;
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}
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#if 0
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case SPU::STQXv16i8:
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case SPU::STQXv8i16:
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case SPU::STQXv4i32:
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case SPU::STQXv4f32:
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case SPU::STQXv2f64:
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case SPU::STQXr128:
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case SPU::STQXr64:
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case SPU::STQXr32:
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case SPU::STQXr16:
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case SPU::STQXr8:
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if (MI->getOperand(1).isReg() && MI->getOperand(2).isReg()
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&& (MI->getOperand(2).getReg() == SPU::R1
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|| MI->getOperand(1).getReg() == SPU::R1)) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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#endif
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}
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return 0;
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}
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@ -445,6 +411,34 @@ void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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}
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}
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//! Return true if the specified load or store can be folded
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bool
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SPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops) const {
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if (Ops.size() != 1) return false;
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// Make sure this is a reg-reg copy.
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unsigned Opc = MI->getOpcode();
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switch (Opc) {
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case SPU::ORv16i8:
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case SPU::ORv8i16:
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case SPU::ORv4i32:
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case SPU::ORv2i64:
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case SPU::ORr8:
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case SPU::ORr16:
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case SPU::ORr32:
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case SPU::ORr64:
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case SPU::ORf32:
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case SPU::ORf64:
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if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
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return true;
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break;
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}
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return false;
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}
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/// foldMemoryOperand - SPU, like PPC, can only fold spills into
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/// copy instructions, turning them into load/store instructions.
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MachineInstr *
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@ -453,38 +447,46 @@ SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const
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{
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#if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
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if (Ops.size() != 1) return NULL;
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if (Ops.size() != 1) return 0;
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unsigned OpNum = Ops[0];
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unsigned Opc = MI->getOpcode();
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MachineInstr *NewMI = 0;
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if ((Opc == SPU::ORr32
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|| Opc == SPU::ORv4i32)
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&& MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
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switch (Opc) {
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case SPU::ORv16i8:
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case SPU::ORv8i16:
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case SPU::ORv4i32:
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case SPU::ORv2i64:
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case SPU::ORr8:
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case SPU::ORr16:
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case SPU::ORr32:
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case SPU::ORr64:
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case SPU::ORf32:
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case SPU::ORf64:
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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bool isKill = MI->getOperand(1).isKill();
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if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
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NewMI = addFrameReference(BuildMI(MF, TII.get(SPU::STQDr32))
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.addReg(InReg, false, false, isKill),
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FrameIndex);
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MachineInstrBuilder MIB = BuildMI(MF, get(SPU::STQDr32));
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MIB.addReg(InReg, false, false, isKill);
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NewMI = addFrameReference(MIB, FrameIndex);
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}
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
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bool isDead = MI->getOperand(0).isDead();
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MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
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MIB.addReg(OutReg, true, false, false, isDead);
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Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
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? SPU::STQDr32 : SPU::STQXr32;
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NewMI = addFrameReference(BuildMI(MF, TII.get(Opc))
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.addReg(OutReg, true, false, false, isDead), FrameIndex);
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}
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NewMI = addFrameReference(MIB, FrameIndex);
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break;
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}
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}
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return NewMI;
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#else
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return 0;
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#endif
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}
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//! Branch analysis
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@ -625,4 +627,38 @@ SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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}
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}
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bool
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SPUInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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return (!MBB.empty() && isUncondBranch(&MBB.back()));
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}
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//! Reverses a branch's condition, returning false on success.
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bool
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SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
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const {
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// Pretty brainless way of inverting the condition, but it works, considering
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// there are only two conditions...
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static struct {
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unsigned Opc; //! The incoming opcode
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unsigned RevCondOpc; //! The reversed condition opcode
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} revconds[] = {
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{ SPU::BRNZr32, SPU::BRZr32 },
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{ SPU::BRNZv4i32, SPU::BRZv4i32 },
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{ SPU::BRZr32, SPU::BRNZr32 },
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{ SPU::BRZv4i32, SPU::BRNZv4i32 },
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{ SPU::BRHNZr16, SPU::BRHZr16 },
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{ SPU::BRHNZv8i16, SPU::BRHZv8i16 },
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{ SPU::BRHZr16, SPU::BRHNZr16 },
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{ SPU::BRHZv8i16, SPU::BRHNZv8i16 }
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};
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unsigned Opc = unsigned(Cond[0].getImm());
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// Pretty dull mapping between the two conditions that SPU can generate:
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for (int i = sizeof(revconds)/sizeof(revconds[0]); i >= 0; --i) {
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if (revconds[i].Opc == Opc) {
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Cond[0].setImm(revconds[i].RevCondOpc);
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return false;
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}
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}
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return true;
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}
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@ -23,6 +23,19 @@ namespace llvm {
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class SPUInstrInfo : public TargetInstrInfoImpl {
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SPUTargetMachine &TM;
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const SPURegisterInfo RI;
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protected:
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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return 0;
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}
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public:
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explicit SPUInstrInfo(SPUTargetMachine &tm);
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@ -34,7 +47,7 @@ namespace llvm {
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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virtual const TargetRegisterClass *getPointerRegClass() const;
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virtual const TargetRegisterClass *getPointerRegClass() const;
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// Return true if the instruction is a register to register move and
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// leave the source and dest operands in the passed parameters.
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@ -47,13 +60,13 @@ namespace llvm {
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int &FrameIndex) const;
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const;
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//! Store a register to a stack slot, based on its register class.
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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@ -77,27 +90,25 @@ namespace llvm {
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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//! Fold spills into load/store instructions
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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//! Fold any load/store to an operand
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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return 0;
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}
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//! Return true if the specified load or store can be folded
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virtual
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bool canFoldMemoryOperand(const MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops) const;
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//! Return true if the specified block does not fall through
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virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
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//! Reverses a branch's condition, returning false on success.
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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@ -1,4 +1,4 @@
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; RUN: llvm-as < %s | llc -march=cellspu -o - | grep brnz
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; RUN: llvm-as < %s | llc -march=cellspu -o - | grep brz
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; PR3274
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target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:64:64-v128:128:128-a0:0:128-s0:128:128"
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