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Allow strict subclasses of register classes, this way we can handle

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ARM instructions with:

foo GPR, rGPR

which happens a lot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112025 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-08-25 04:58:56 +00:00
parent 7226a0eb52
commit 53452606ca
1 changed files with 3 additions and 2 deletions
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5
utils/TableGen/FastISelEmitter.cpp
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@ -112,9 +112,10 @@ struct OperandsSignature {
if (!RC)
return false;
// For now, all the operands must have the same register class.
// For now, all the operands must have the same register class or be
// a strict subclass of the destination.
if (DstRC) {
if (DstRC != RC)
if (DstRC != RC && !DstRC->hasSubClass(RC))
return false;
} else
DstRC = RC;