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Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-01-22 09:10:11 +00:00
parent e70909b8c9
commit 536ab130ec
7 changed files with 13 additions and 148 deletions
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utils/TableGen/FastISelEmitter.cpp
+3 -2
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@@ -440,7 +440,8 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
Operands.PrintArguments(OS, *Memo.PhysRegs);
OS << ");\n";
} else {
OS << "extractsubreg(Op0, ";
OS << "extractsubreg(" << getName(RetVT);
OS << ", Op0, ";
OS << (unsigned)Memo.SubRegNo;
OS << ");\n";
}
@@ -534,7 +535,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
Operands.PrintArguments(OS, *Memo.PhysRegs);
OS << ");\n";
} else {
OS << "extractsubreg(Op0, ";
OS << "extractsubreg(RetVT, Op0, ";
OS << (unsigned)Memo.SubRegNo;
OS << ");\n";
}