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ARM STR(immediate) assembly parsing and encoding.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-11 19:22:40 +00:00
parent 71156a6e00
commit 548340c4bf
4 changed files with 36 additions and 6 deletions
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5
lib/Target/ARM/ARMInstrInfo.td
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@ -2191,11 +2191,12 @@ multiclass AI2_stridx<bit isByte, string opc, InstrItinClass itin> {
let Inst{23} = addr{12}; // U (add = ('U' == 1))
let Inst{19-16} = addr{16-13}; // Rn
let Inst{11-0} = addr{11-0}; // imm12
let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
}
def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addrmode2:$addr), IndexModePre, StFrm, itin,
(ins GPR:$Rt, ldst_so_reg:$addr),
IndexModePre, StFrm, itin,
opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
bits<17> addr;
let Inst{25} = 1;

20
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -119,6 +119,8 @@ class ARMAsmParser : public MCTargetAsmParser {
// Asm Match Converter Methods
bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
const SmallVectorImpl<MCParsedAsmOperand*> &);
bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
const SmallVectorImpl<MCParsedAsmOperand*> &);
bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
const SmallVectorImpl<MCParsedAsmOperand*> &);
bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
@ -2100,6 +2102,20 @@ cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
return true;
}
/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
bool ARMAsmParser::
cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
return true;
}
/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
@ -2108,7 +2124,9 @@ cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
assert(0 && "cvtStWriteBackRegAddrMode2 not implemented yet!");
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
return true;
}

14
test/MC/ARM/arm-memory-instructions.s
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@ -293,3 +293,17 @@ _func:
@ CHECK: ldrsht r2, [r1], -r4 @ encoding: [0xf4,0x20,0x31,0xe0]
@------------------------------------------------------------------------------
@ STR (immediate)
@------------------------------------------------------------------------------
str r8, [r12]
str r7, [r1, #12]
str r3, [r5, #40]!
str r9, [sp], #4095
str r1, [r7], #-128
@ CHECK: str r8, [r12] @ encoding: [0x00,0x80,0x8c,0xe5]
@ CHECK: str r7, [r1, #12] @ encoding: [0x0c,0x70,0x81,0xe5]
@ CHECK: str r3, [r5, #40]! @ encoding: [0x28,0x30,0xa5,0xe5]
@ CHECK: str r9, [sp], #4095 @ encoding: [0xff,0x9f,0x8d,0xe4]
@ CHECK: str r1, [r7], #-128 @ encoding: [0x80,0x10,0x07,0xe4]

3
test/MC/ARM/basic-arm-instructions.s
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@ -1854,9 +1854,6 @@ Lforward:
@ CHECK: stmdb r0!, {r1, r5, r7, sp} @ encoding: [0xa2,0x20,0x20,0xe9]
@------------------------------------------------------------------------------
@ FIXME:STR*
@------------------------------------------------------------------------------
@------------------------------------------------------------------------------
@ STREX/STREXB/STREXH/STREXD
@------------------------------------------------------------------------------