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Add X86 ANDN instruction. Including instruction selection.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2011-10-14 07:06:56 +00:00
parent 909652f687
commit 54a11176f6
8 changed files with 82 additions and 2 deletions
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20
lib/Target/X86/X86ISelLowering.cpp
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@ -10702,6 +10702,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
case X86ISD::OR: return "X86ISD::OR";
case X86ISD::XOR: return "X86ISD::XOR";
case X86ISD::AND: return "X86ISD::AND";
case X86ISD::ANDN: return "X86ISD::ANDN";
case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
case X86ISD::PTEST: return "X86ISD::PTEST";
case X86ISD::TESTP: return "X86ISD::TESTP";
@ -13295,11 +13296,28 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
if (R.getNode())
return R;
EVT VT = N->getValueType(0);
// Create ANDN instructions
if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
DebugLoc DL = N->getDebugLoc();
// Check LHS for not
if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
// Check RHS for not
if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
return SDValue();
}
// Want to form ANDNP nodes:
// 1) In the hopes of then easily combining them with OR and AND nodes
// to form PBLEND/PSIGN.
// 2) To match ANDN packed intrinsics
EVT VT = N->getValueType(0);
if (VT != MVT::v2i64 && VT != MVT::v4i64)
return SDValue();

2
lib/Target/X86/X86ISelLowering.h
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@ -228,6 +228,8 @@ namespace llvm {
ADD, SUB, ADC, SBB, SMUL,
INC, DEC, OR, XOR, AND,
ANDN, // ANDN - Bitwise AND NOT with FLAGS results.
UMUL, // LOW, HI, FLAGS = umul LHS, RHS
// MUL_IMM - X86 specific multiply by immediate.

20
lib/Target/X86/X86InstrArithmetic.td
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@ -1151,5 +1151,23 @@ let Defs = [EFLAGS] in {
let isPseudo = 1 in
def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask),
"", []>;
}
}
//===----------------------------------------------------------------------===//
// ANDN Instruction
//
multiclass bmi_andn<string mnemonic, RegisterClass RC, X86MemOperand x86memop,
PatFrag ld_frag> {
def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set RC:$dst, EFLAGS, (X86andn_flag RC:$src1, RC:$src2))]>;
def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set RC:$dst, EFLAGS,
(X86andn_flag RC:$src1, (ld_frag addr:$src2)))]>;
}
let Predicates = [HasBMI], Defs = [EFLAGS] in {
defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8, VEX_4V;
defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8, VEX_4V, VEX_W;
}

1
lib/Target/X86/X86InstrInfo.td
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@ -224,6 +224,7 @@ def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
[SDNPCommutative]>;
def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
[SDNPCommutative]>;
def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;

15
test/CodeGen/X86/bmi.ll
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@ -36,3 +36,18 @@ define i8 @t4(i8 %x) nounwind {
declare i8 @llvm.cttz.i8(i8) nounwind readnone
define i32 @andn32(i32 %x, i32 %y) nounwind readnone {
%tmp1 = xor i32 %x, -1
%tmp2 = and i32 %y, %tmp1
ret i32 %tmp2
; CHECK: andn32:
; CHECK: andnl
}
define i64 @andn64(i64 %x, i64 %y) nounwind readnone {
%tmp1 = xor i64 %x, -1
%tmp2 = and i64 %tmp1, %y
ret i64 %tmp2
; CHECK: andn64:
; CHECK: andnq
}

12
test/MC/Disassembler/X86/simple-tests.txt
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@ -506,3 +506,15 @@
# CHECK: tzcntq %rax, %rax
0xf3 0x48 0x0f 0xbc 0xc0
# CHECK: andnl %ecx, %r15d, %eax
0xc4 0xe2 0x00 0xf2 0xc1
# CHECK: andnq %rax, %r15, %rax
0xc4 0xe2 0x80 0xf2 0xc0
# CHECK: andnl (%rax), %r15d, %eax
0xc4 0xe2 0x00 0xf2 0x00
# CHECK: andnq (%rax), %r15, %rax
0xc4 0xe2 0x80 0xf2 0x00

12
test/MC/Disassembler/X86/x86-32.txt
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@ -483,3 +483,15 @@
# CHECK: tzcntw %ax, %ax
0x66 0xf3 0x0f 0xbc 0xc0
# CHECK: andnl %ecx, %edi, %eax
0xc4 0xe2 0x00 0xf2 0xc1
# CHECK: andnl (%eax), %edi, %eax
0xc4 0xe2 0x00 0xf2 0x00
# CHECK: andnl %ecx, %edi, %eax
0xc4 0xe2 0x80 0xf2 0xc1
# CHECK: andnl (%eax), %edi, %eax
0xc4 0xe2 0x80 0xf2 0x00

2
utils/TableGen/X86RecognizableInstr.cpp
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@ -1142,6 +1142,8 @@ OperandEncoding RecognizableInstr::roRegisterEncodingFromString
OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
(const std::string &s,
bool hasOpSizePrefix) {
ENCODING("GR32", ENCODING_VVVV)
ENCODING("GR64", ENCODING_VVVV)
ENCODING("FR32", ENCODING_VVVV)
ENCODING("FR64", ENCODING_VVVV)
ENCODING("VR128", ENCODING_VVVV)