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When legalizing brcond ->brcc or select -> selectcc, make sure to truncate

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the old condition to a one bit value.  The incoming value must have been
promoted, and the top bits are undefined.  This causes us to generate:

_test:
        rlwinm r2, r3, 0, 31, 31
        li r3, 17
        cmpwi cr0, r2, 0
        bne .LBB_test_2 ;
.LBB_test_1:    ;
        li r3, 1
.LBB_test_2:    ;
        blr

instead of:

_test:
        rlwinm r2, r3, 0, 31, 31
        li r2, 17
        cmpwi cr0, r3, 0
        bne .LBB_test_2 ;
.LBB_test_1:    ;
        li r2, 1
.LBB_test_2:    ;
        or r3, r2, r2
        blr

for:

int %test(bool %c) {
        %retval = select bool %c, int 17, int 1
        ret int %retval
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22947 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-21 18:03:09 +00:00
parent 4dd4a2d278
commit 550b1e59c4
1 changed files with 7 additions and 0 deletions
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7
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -681,6 +681,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
Tmp2.getOperand(0), Tmp2.getOperand(1),
Node->getOperand(2));
} else {
// Make sure the condition is either zero or one. It may have been
// promoted from something else.
Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
DAG.getCondCode(ISD::SETNE), Tmp2,
DAG.getConstant(0, Tmp2.getValueType()),
@ -1072,6 +1076,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
Tmp2, Tmp3,
cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
} else {
// Make sure the condition is either zero or one. It may have been
// promoted from something else.
Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
Result = DAG.getSelectCC(Tmp1,
DAG.getConstant(0, Tmp1.getValueType()),
Tmp2, Tmp3, ISD::SETNE);