6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-25 00:24:26 +00:00
Code Issues Projects Releases Wiki Activity

Rename MachineCodeForBasicBlock to MachineBasicBlock

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4318 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2002-10-28 01:41:47 +00:00
parent 32be9f6cd4
commit 55291ead55
16 changed files with 81 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
lib/Analysis/LiveVar/BBLiveVar.cpp
View File

@ -7,10 +7,9 @@
#include "BBLiveVar.h" #include "BBLiveVar.h"
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Support/CFG.h" #include "llvm/Support/CFG.h"
#include "Support/SetOperations.h" #include "Support/SetOperations.h"
#include <iostream>
/// BROKEN: Should not include sparc stuff directly into here /// BROKEN: Should not include sparc stuff directly into here
#include "../../Target/Sparc/SparcInternals.h" // Only for PHI defn #include "../../Target/Sparc/SparcInternals.h" // Only for PHI defn
@ -51,10 +50,10 @@ BBLiveVar::BBLiveVar(const BasicBlock &bb, unsigned id)
void BBLiveVar::calcDefUseSets() { void BBLiveVar::calcDefUseSets() {
// get the iterator for machine instructions // get the iterator for machine instructions
const MachineCodeForBasicBlock &MIVec = MachineCodeForBasicBlock::get(&BB); const MachineBasicBlock &MIVec = MachineBasicBlock::get(&BB);
// iterate over all the machine instructions in BB // iterate over all the machine instructions in BB
for (MachineCodeForBasicBlock::const_reverse_iterator MII = MIVec.rbegin(), for (MachineBasicBlock::const_reverse_iterator MII = MIVec.rbegin(),
MIE = MIVec.rend(); MII != MIE; ++MII) { MIE = MIVec.rend(); MII != MIE; ++MII) {
const MachineInstr *MI = *MII; const MachineInstr *MI = *MII;

7
lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp
View File

@ -8,12 +8,11 @@
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
#include "BBLiveVar.h" #include "BBLiveVar.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Support/CFG.h" #include "llvm/Support/CFG.h"
#include "Support/PostOrderIterator.h" #include "Support/PostOrderIterator.h"
#include "Support/SetOperations.h" #include "Support/SetOperations.h"
#include "Support/CommandLine.h" #include "Support/CommandLine.h"
#include <iostream>
static RegisterAnalysis<FunctionLiveVarInfo> static RegisterAnalysis<FunctionLiveVarInfo>
X("livevar", "Live Variable Analysis"); X("livevar", "Live Variable Analysis");
@ -241,7 +240,7 @@ static void applyTranferFuncForMInst(ValueSet &LVS, const MachineInstr *MInst) {
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) { void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) {
const MachineCodeForBasicBlock &MIVec = MachineCodeForBasicBlock::get(BB); const MachineBasicBlock &MIVec = MachineBasicBlock::get(BB);
if (DEBUG_LV >= LV_DEBUG_Instr) if (DEBUG_LV >= LV_DEBUG_Instr)
std::cerr << "\n======For BB " << BB->getName() std::cerr << "\n======For BB " << BB->getName()
@ -252,7 +251,7 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) {
set_union(CurSet, *SetAI); // CurSet now contains OutSet set_union(CurSet, *SetAI); // CurSet now contains OutSet
// iterate over all the machine instructions in BB // iterate over all the machine instructions in BB
for (MachineCodeForBasicBlock::const_reverse_iterator MII = MIVec.rbegin(), for (MachineBasicBlock::const_reverse_iterator MII = MIVec.rbegin(),
MIE = MIVec.rend(); MII != MIE; ++MII) { MIE = MIVec.rend(); MII != MIE; ++MII) {
// MI is cur machine inst // MI is cur machine inst
const MachineInstr *MI = *MII; const MachineInstr *MI = *MII;

14
lib/CodeGen/InstrSched/InstrScheduling.cpp
View File

@ -8,7 +8,7 @@
#include "SchedPriorities.h" #include "SchedPriorities.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
@ -631,14 +631,14 @@ AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue)
static void static void
RecordSchedule(const BasicBlock* bb, const SchedulingManager& S) RecordSchedule(const BasicBlock* bb, const SchedulingManager& S)
{ {
MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb); MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
const MachineInstrInfo& mii = S.schedInfo.getInstrInfo(); const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
#ifndef NDEBUG #ifndef NDEBUG
// Lets make sure we didn't lose any instructions, except possibly // Lets make sure we didn't lose any instructions, except possibly
// some NOPs from delay slots. Also, PHIs are not included in the schedule. // some NOPs from delay slots. Also, PHIs are not included in the schedule.
unsigned numInstr = 0; unsigned numInstr = 0;
for (MachineCodeForBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I) for (MachineBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I)
if (! mii.isNop((*I)->getOpCode()) && if (! mii.isNop((*I)->getOpCode()) &&
! mii.isDummyPhiInstr((*I)->getOpCode())) ! mii.isDummyPhiInstr((*I)->getOpCode()))
++numInstr; ++numInstr;
@ -650,7 +650,7 @@ RecordSchedule(const BasicBlock* bb, const SchedulingManager& S)
return; // empty basic block! return; // empty basic block!
// First find the dummy instructions at the start of the basic block // First find the dummy instructions at the start of the basic block
MachineCodeForBasicBlock::iterator I = mvec.begin(); MachineBasicBlock::iterator I = mvec.begin();
for ( ; I != mvec.end(); ++I) for ( ; I != mvec.end(); ++I)
if (! mii.isDummyPhiInstr((*I)->getOpCode())) if (! mii.isDummyPhiInstr((*I)->getOpCode()))
break; break;
@ -1220,7 +1220,7 @@ ReplaceNopsWithUsefulInstr(SchedulingManager& S,
// fill delay slots, otherwise, just discard them. // fill delay slots, otherwise, just discard them.
// //
unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1; unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(node->getBB()); MachineBasicBlock& bbMvec = MachineBasicBlock::get(node->getBB());
assert(bbMvec[firstDelaySlotIdx - 1] == brInstr && assert(bbMvec[firstDelaySlotIdx - 1] == brInstr &&
"Incorrect instr. index in basic block for brInstr"); "Incorrect instr. index in basic block for brInstr");
@ -1325,8 +1325,8 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S,
// Simply passing in an empty delayNodeVec will have this effect. // Simply passing in an empty delayNodeVec will have this effect.
// //
delayNodeVec.clear(); delayNodeVec.clear();
const MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(bb); const MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb);
for (unsigned i=0; i < bbMvec.size(); i++) for (unsigned i=0; i < bbMvec.size(); ++i)
if (bbMvec[i] != brInstr && if (bbMvec[i] != brInstr &&
mii.getNumDelaySlots(bbMvec[i]->getOpCode()) > 0) mii.getNumDelaySlots(bbMvec[i]->getOpCode()) > 0)
{ {

12
lib/CodeGen/InstrSched/SchedGraph.cpp
View File

@ -9,7 +9,7 @@
#include "SchedGraph.h" #include "SchedGraph.h"
#include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Target/MachineRegInfo.h" #include "llvm/Target/MachineRegInfo.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Function.h" #include "llvm/Function.h"
@ -387,7 +387,7 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
// all preceding instructions in the basic block. Use 0 latency again. // all preceding instructions in the basic block. Use 0 latency again.
// //
const BasicBlock* bb = firstBrNode->getBB(); const BasicBlock* bb = firstBrNode->getBB();
const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb); const MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
for (unsigned i=0, N=mvec.size(); i < N; i++) for (unsigned i=0, N=mvec.size(); i < N; i++)
{ {
if (mvec[i] == termMvec[first]) // reached the first branch if (mvec[i] == termMvec[first]) // reached the first branch
@ -480,7 +480,7 @@ SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
// //
void void
SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec, SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
MachineCodeForBasicBlock& bbMvec, MachineBasicBlock& bbMvec,
const TargetMachine& target) const TargetMachine& target)
{ {
const MachineInstrInfo& mii = target.getInstrInfo(); const MachineInstrInfo& mii = target.getInstrInfo();
@ -753,7 +753,7 @@ SchedGraph::buildNodesforBB(const TargetMachine& target,
// Build graph nodes for each VM instruction and gather def/use info. // Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions. // Do both those together in a single pass over all machine instructions.
const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb); const MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
for (unsigned i=0; i < mvec.size(); i++) for (unsigned i=0; i < mvec.size(); i++)
if (! mii.isDummyPhiInstr(mvec[i]->getOpCode())) if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
{ {
@ -789,7 +789,7 @@ SchedGraph::buildNodesforBB(const TargetMachine& target,
// Find the machine instruction that makes a copy of inval to (*PI). // Find the machine instruction that makes a copy of inval to (*PI).
// This must be in the current basic block (bb). // This must be in the current basic block (bb).
const MachineCodeForVMInstr& mvec = MachineCodeForBasicBlock::get(*PI); const MachineCodeForVMInstr& mvec = MachineBasicBlock::get(*PI);
const MachineInstr* theCopy = NULL; const MachineInstr* theCopy = NULL;
for (unsigned i=0; i < mvec.size() && theCopy == NULL; i++) for (unsigned i=0; i < mvec.size() && theCopy == NULL; i++)
if (! mii.isDummyPhiInstr(mvec[i]->getOpCode())) if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
@ -882,7 +882,7 @@ SchedGraph::buildGraph(const TargetMachine& target)
// //
//---------------------------------------------------------------- //----------------------------------------------------------------
MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(bb); MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb);
// First, add edges to the terminator instruction of the basic block. // First, add edges to the terminator instruction of the basic block.
this->addCDEdges(bb->getTerminator(), target); this->addCDEdges(bb->getTerminator(), target);

10
lib/CodeGen/InstrSelection/InstrSelection.cpp
View File

@ -11,7 +11,7 @@
#include "llvm/CodeGen/InstrSelectionSupport.h" #include "llvm/CodeGen/InstrSelectionSupport.h"
#include "llvm/CodeGen/InstrForest.h" #include "llvm/CodeGen/InstrForest.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/MachineRegInfo.h" #include "llvm/Target/MachineRegInfo.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
@ -145,7 +145,7 @@ bool InstructionSelection::runOnFunction(Function &F)
for (Function::iterator BI = F.begin(), BE = F.end(); BI != BE; ++BI) for (Function::iterator BI = F.begin(), BE = F.end(); BI != BE; ++BI)
for (BasicBlock::iterator II = BI->begin(); II != BI->end(); ++II) { for (BasicBlock::iterator II = BI->begin(); II != BI->end(); ++II) {
MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(II); MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(II);
MachineCodeForBasicBlock &MCBB = MachineCodeForBasicBlock::get(BI); MachineBasicBlock &MCBB = MachineBasicBlock::get(BI);
MCBB.insert(MCBB.end(), mvec.begin(), mvec.end()); MCBB.insert(MCBB.end(), mvec.begin(), mvec.end());
} }
@ -205,7 +205,7 @@ InstructionSelection::InsertCodeForPhis(Function &F)
Target.getRegInfo().cpValue2Value(PhiCpRes, PN, mvec); Target.getRegInfo().cpValue2Value(PhiCpRes, PN, mvec);
// get an iterator to machine instructions in the BB // get an iterator to machine instructions in the BB
MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(BB); MachineBasicBlock& bbMvec = MachineBasicBlock::get(BB);
bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end()); bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end());
} // for each Phi Instr in BB } // for each Phi Instr in BB
@ -227,11 +227,11 @@ InstructionSelection::InsertPhiElimInstructions(BasicBlock *BB,
assert (FirstMIOfTerm && "No Machine Instrs for terminator"); assert (FirstMIOfTerm && "No Machine Instrs for terminator");
MachineCodeForBasicBlock &bbMvec = MachineCodeForBasicBlock::get(BB); MachineBasicBlock &bbMvec = MachineBasicBlock::get(BB);
// find the position of first machine instruction generated by the // find the position of first machine instruction generated by the
// terminator of this BB // terminator of this BB
MachineCodeForBasicBlock::iterator MCIt = MachineBasicBlock::iterator MCIt =
std::find(bbMvec.begin(), bbMvec.end(), FirstMIOfTerm); std::find(bbMvec.begin(), bbMvec.end(), FirstMIOfTerm);
assert( MCIt != bbMvec.end() && "Start inst of terminator not found"); assert( MCIt != bbMvec.end() && "Start inst of terminator not found");

4
lib/CodeGen/MachineBasicBlock.cpp
View File

@ -1,10 +1,10 @@
//===-- MachineCodeForBasicBlock.cpp --------------------------------------===// //===-- MachineBasicBlock.cpp ---------------------------------------------===//
// //
// Collect the sequence of machine instructions for a basic block. // Collect the sequence of machine instructions for a basic block.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
AnnotationID MCFBB_AID( AnnotationID MCFBB_AID(
AnnotationManager::getID("CodeGen::MachineBasicBlock")); AnnotationManager::getID("CodeGen::MachineBasicBlock"));

4
lib/CodeGen/MachineFunction.cpp
View File

@ -8,7 +8,7 @@
#include "llvm/CodeGen/MachineInstr.h" // For debug output #include "llvm/CodeGen/MachineInstr.h" // For debug output
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineFrameInfo.h" #include "llvm/Target/MachineFrameInfo.h"
@ -303,7 +303,7 @@ MachineFunction::dump() const
{ {
std::cerr << "\n" << BB->getName() << " (" << (const void*)BB std::cerr << "\n" << BB->getName() << " (" << (const void*)BB
<< ")" << ":" << "\n"; << ")" << ":" << "\n";
MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(BB); MachineBasicBlock& mvec = MachineBasicBlock::get(BB);
for (unsigned i=0; i < mvec.size(); i++) for (unsigned i=0; i < mvec.size(); i++)
std::cerr << "\t" << *mvec[i]; std::cerr << "\t" << *mvec[i];
} }

14
lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
View File

@ -8,7 +8,7 @@
#include "SchedPriorities.h" #include "SchedPriorities.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
@ -631,14 +631,14 @@ AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue)
static void static void
RecordSchedule(const BasicBlock* bb, const SchedulingManager& S) RecordSchedule(const BasicBlock* bb, const SchedulingManager& S)
{ {
MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb); MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
const MachineInstrInfo& mii = S.schedInfo.getInstrInfo(); const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
#ifndef NDEBUG #ifndef NDEBUG
// Lets make sure we didn't lose any instructions, except possibly // Lets make sure we didn't lose any instructions, except possibly
// some NOPs from delay slots. Also, PHIs are not included in the schedule. // some NOPs from delay slots. Also, PHIs are not included in the schedule.
unsigned numInstr = 0; unsigned numInstr = 0;
for (MachineCodeForBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I) for (MachineBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I)
if (! mii.isNop((*I)->getOpCode()) && if (! mii.isNop((*I)->getOpCode()) &&
! mii.isDummyPhiInstr((*I)->getOpCode())) ! mii.isDummyPhiInstr((*I)->getOpCode()))
++numInstr; ++numInstr;
@ -650,7 +650,7 @@ RecordSchedule(const BasicBlock* bb, const SchedulingManager& S)
return; // empty basic block! return; // empty basic block!
// First find the dummy instructions at the start of the basic block // First find the dummy instructions at the start of the basic block
MachineCodeForBasicBlock::iterator I = mvec.begin(); MachineBasicBlock::iterator I = mvec.begin();
for ( ; I != mvec.end(); ++I) for ( ; I != mvec.end(); ++I)
if (! mii.isDummyPhiInstr((*I)->getOpCode())) if (! mii.isDummyPhiInstr((*I)->getOpCode()))
break; break;
@ -1220,7 +1220,7 @@ ReplaceNopsWithUsefulInstr(SchedulingManager& S,
// fill delay slots, otherwise, just discard them. // fill delay slots, otherwise, just discard them.
// //
unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1; unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(node->getBB()); MachineBasicBlock& bbMvec = MachineBasicBlock::get(node->getBB());
assert(bbMvec[firstDelaySlotIdx - 1] == brInstr && assert(bbMvec[firstDelaySlotIdx - 1] == brInstr &&
"Incorrect instr. index in basic block for brInstr"); "Incorrect instr. index in basic block for brInstr");
@ -1325,8 +1325,8 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S,
// Simply passing in an empty delayNodeVec will have this effect. // Simply passing in an empty delayNodeVec will have this effect.
// //
delayNodeVec.clear(); delayNodeVec.clear();
const MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(bb); const MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb);
for (unsigned i=0; i < bbMvec.size(); i++) for (unsigned i=0; i < bbMvec.size(); ++i)
if (bbMvec[i] != brInstr && if (bbMvec[i] != brInstr &&
mii.getNumDelaySlots(bbMvec[i]->getOpCode()) > 0) mii.getNumDelaySlots(bbMvec[i]->getOpCode()) > 0)
{ {

12
lib/Target/SparcV9/InstrSched/SchedGraph.cpp
View File

@ -9,7 +9,7 @@
#include "SchedGraph.h" #include "SchedGraph.h"
#include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Target/MachineRegInfo.h" #include "llvm/Target/MachineRegInfo.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Function.h" #include "llvm/Function.h"
@ -387,7 +387,7 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
// all preceding instructions in the basic block. Use 0 latency again. // all preceding instructions in the basic block. Use 0 latency again.
// //
const BasicBlock* bb = firstBrNode->getBB(); const BasicBlock* bb = firstBrNode->getBB();
const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb); const MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
for (unsigned i=0, N=mvec.size(); i < N; i++) for (unsigned i=0, N=mvec.size(); i < N; i++)
{ {
if (mvec[i] == termMvec[first]) // reached the first branch if (mvec[i] == termMvec[first]) // reached the first branch
@ -480,7 +480,7 @@ SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
// //
void void
SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec, SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
MachineCodeForBasicBlock& bbMvec, MachineBasicBlock& bbMvec,
const TargetMachine& target) const TargetMachine& target)
{ {
const MachineInstrInfo& mii = target.getInstrInfo(); const MachineInstrInfo& mii = target.getInstrInfo();
@ -753,7 +753,7 @@ SchedGraph::buildNodesforBB(const TargetMachine& target,
// Build graph nodes for each VM instruction and gather def/use info. // Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions. // Do both those together in a single pass over all machine instructions.
const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb); const MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
for (unsigned i=0; i < mvec.size(); i++) for (unsigned i=0; i < mvec.size(); i++)
if (! mii.isDummyPhiInstr(mvec[i]->getOpCode())) if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
{ {
@ -789,7 +789,7 @@ SchedGraph::buildNodesforBB(const TargetMachine& target,
// Find the machine instruction that makes a copy of inval to (*PI). // Find the machine instruction that makes a copy of inval to (*PI).
// This must be in the current basic block (bb). // This must be in the current basic block (bb).
const MachineCodeForVMInstr& mvec = MachineCodeForBasicBlock::get(*PI); const MachineCodeForVMInstr& mvec = MachineBasicBlock::get(*PI);
const MachineInstr* theCopy = NULL; const MachineInstr* theCopy = NULL;
for (unsigned i=0; i < mvec.size() && theCopy == NULL; i++) for (unsigned i=0; i < mvec.size() && theCopy == NULL; i++)
if (! mii.isDummyPhiInstr(mvec[i]->getOpCode())) if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
@ -882,7 +882,7 @@ SchedGraph::buildGraph(const TargetMachine& target)
// //
//---------------------------------------------------------------- //----------------------------------------------------------------
MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(bb); MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb);
// First, add edges to the terminator instruction of the basic block. // First, add edges to the terminator instruction of the basic block.
this->addCDEdges(bb->getTerminator(), target); this->addCDEdges(bb->getTerminator(), target);

10
lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
View File

@ -11,7 +11,7 @@
#include "llvm/CodeGen/InstrSelectionSupport.h" #include "llvm/CodeGen/InstrSelectionSupport.h"
#include "llvm/CodeGen/InstrForest.h" #include "llvm/CodeGen/InstrForest.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/MachineRegInfo.h" #include "llvm/Target/MachineRegInfo.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
@ -145,7 +145,7 @@ bool InstructionSelection::runOnFunction(Function &F)
for (Function::iterator BI = F.begin(), BE = F.end(); BI != BE; ++BI) for (Function::iterator BI = F.begin(), BE = F.end(); BI != BE; ++BI)
for (BasicBlock::iterator II = BI->begin(); II != BI->end(); ++II) { for (BasicBlock::iterator II = BI->begin(); II != BI->end(); ++II) {
MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(II); MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(II);
MachineCodeForBasicBlock &MCBB = MachineCodeForBasicBlock::get(BI); MachineBasicBlock &MCBB = MachineBasicBlock::get(BI);
MCBB.insert(MCBB.end(), mvec.begin(), mvec.end()); MCBB.insert(MCBB.end(), mvec.begin(), mvec.end());
} }
@ -205,7 +205,7 @@ InstructionSelection::InsertCodeForPhis(Function &F)
Target.getRegInfo().cpValue2Value(PhiCpRes, PN, mvec); Target.getRegInfo().cpValue2Value(PhiCpRes, PN, mvec);
// get an iterator to machine instructions in the BB // get an iterator to machine instructions in the BB
MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(BB); MachineBasicBlock& bbMvec = MachineBasicBlock::get(BB);
bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end()); bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end());
} // for each Phi Instr in BB } // for each Phi Instr in BB
@ -227,11 +227,11 @@ InstructionSelection::InsertPhiElimInstructions(BasicBlock *BB,
assert (FirstMIOfTerm && "No Machine Instrs for terminator"); assert (FirstMIOfTerm && "No Machine Instrs for terminator");
MachineCodeForBasicBlock &bbMvec = MachineCodeForBasicBlock::get(BB); MachineBasicBlock &bbMvec = MachineBasicBlock::get(BB);
// find the position of first machine instruction generated by the // find the position of first machine instruction generated by the
// terminator of this BB // terminator of this BB
MachineCodeForBasicBlock::iterator MCIt = MachineBasicBlock::iterator MCIt =
std::find(bbMvec.begin(), bbMvec.end(), FirstMIOfTerm); std::find(bbMvec.begin(), bbMvec.end(), FirstMIOfTerm);
assert( MCIt != bbMvec.end() && "Start inst of terminator not found"); assert( MCIt != bbMvec.end() && "Start inst of terminator not found");

7
lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
View File

@ -7,10 +7,9 @@
#include "BBLiveVar.h" #include "BBLiveVar.h"
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Support/CFG.h" #include "llvm/Support/CFG.h"
#include "Support/SetOperations.h" #include "Support/SetOperations.h"
#include <iostream>
/// BROKEN: Should not include sparc stuff directly into here /// BROKEN: Should not include sparc stuff directly into here
#include "../../Target/Sparc/SparcInternals.h" // Only for PHI defn #include "../../Target/Sparc/SparcInternals.h" // Only for PHI defn
@ -51,10 +50,10 @@ BBLiveVar::BBLiveVar(const BasicBlock &bb, unsigned id)
void BBLiveVar::calcDefUseSets() { void BBLiveVar::calcDefUseSets() {
// get the iterator for machine instructions // get the iterator for machine instructions
const MachineCodeForBasicBlock &MIVec = MachineCodeForBasicBlock::get(&BB); const MachineBasicBlock &MIVec = MachineBasicBlock::get(&BB);
// iterate over all the machine instructions in BB // iterate over all the machine instructions in BB
for (MachineCodeForBasicBlock::const_reverse_iterator MII = MIVec.rbegin(), for (MachineBasicBlock::const_reverse_iterator MII = MIVec.rbegin(),
MIE = MIVec.rend(); MII != MIE; ++MII) { MIE = MIVec.rend(); MII != MIE; ++MII) {
const MachineInstr *MI = *MII; const MachineInstr *MI = *MII;

7
lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
View File

@ -8,12 +8,11 @@
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
#include "BBLiveVar.h" #include "BBLiveVar.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Support/CFG.h" #include "llvm/Support/CFG.h"
#include "Support/PostOrderIterator.h" #include "Support/PostOrderIterator.h"
#include "Support/SetOperations.h" #include "Support/SetOperations.h"
#include "Support/CommandLine.h" #include "Support/CommandLine.h"
#include <iostream>
static RegisterAnalysis<FunctionLiveVarInfo> static RegisterAnalysis<FunctionLiveVarInfo>
X("livevar", "Live Variable Analysis"); X("livevar", "Live Variable Analysis");
@ -241,7 +240,7 @@ static void applyTranferFuncForMInst(ValueSet &LVS, const MachineInstr *MInst) {
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) { void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) {
const MachineCodeForBasicBlock &MIVec = MachineCodeForBasicBlock::get(BB); const MachineBasicBlock &MIVec = MachineBasicBlock::get(BB);
if (DEBUG_LV >= LV_DEBUG_Instr) if (DEBUG_LV >= LV_DEBUG_Instr)
std::cerr << "\n======For BB " << BB->getName() std::cerr << "\n======For BB " << BB->getName()
@ -252,7 +251,7 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) {
set_union(CurSet, *SetAI); // CurSet now contains OutSet set_union(CurSet, *SetAI); // CurSet now contains OutSet
// iterate over all the machine instructions in BB // iterate over all the machine instructions in BB
for (MachineCodeForBasicBlock::const_reverse_iterator MII = MIVec.rbegin(), for (MachineBasicBlock::const_reverse_iterator MII = MIVec.rbegin(),
MIE = MIVec.rend(); MII != MIE; ++MII) { MIE = MIVec.rend(); MII != MIE; ++MII) {
// MI is cur machine inst // MI is cur machine inst
const MachineInstr *MI = *MII; const MachineInstr *MI = *MII;

10
lib/Target/SparcV9/MappingInfo.cpp
View File

@ -10,7 +10,7 @@
#include "llvm/Pass.h" #include "llvm/Pass.h"
#include "llvm/Module.h" #include "llvm/Module.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineCodeForInstruction.h"
#include <map> #include <map>
using std::vector; using std::vector;
@ -126,7 +126,7 @@ void getMappingInfoForFunction::create_BB_to_MInumber_Key(Function &FI){
unsigned i = 0; unsigned i = 0;
for (Function::iterator BI = FI.begin(), BE = FI.end(); for (Function::iterator BI = FI.begin(), BE = FI.end();
BI != BE; ++BI){ BI != BE; ++BI){
MachineCodeForBasicBlock &miBB = MachineCodeForBasicBlock::get(BI); MachineBasicBlock &miBB = MachineBasicBlock::get(BI);
BBkey[miBB[0]] = i; BBkey[miBB[0]] = i;
i = i+(miBB.size()); i = i+(miBB.size());
} }
@ -136,9 +136,9 @@ void getMappingInfoForFunction::create_BB_to_MInumber_Key(Function &FI){
void getMappingInfoForFunction::create_MI_to_number_Key(Function &FI){ void getMappingInfoForFunction::create_MI_to_number_Key(Function &FI){
for (Function::iterator BI=FI.begin(), BE=FI.end(); for (Function::iterator BI=FI.begin(), BE=FI.end();
BI != BE; ++BI){ BI != BE; ++BI){
MachineCodeForBasicBlock &miBB = MachineCodeForBasicBlock::get(BI); MachineBasicBlock &miBB = MachineBasicBlock::get(BI);
unsigned j = 0; unsigned j = 0;
for(MachineCodeForBasicBlock::iterator miI=miBB.begin(), miE=miBB.end(); for(MachineBasicBlock::iterator miI=miBB.begin(), miE=miBB.end();
miI!=miE; ++miI, ++j){ miI!=miE; ++miI, ++j){
MIkey[*miI]=j; MIkey[*miI]=j;
} }
@ -151,7 +151,7 @@ void getMappingInfoForFunction::writeBBToMImap(Function &FI){
unsigned bb=0; unsigned bb=0;
for (Function::iterator BI = FI.begin(), for (Function::iterator BI = FI.begin(),
BE = FI.end(); BI != BE; ++BI, ++bb){ BE = FI.end(); BI != BE; ++BI, ++bb){
MachineCodeForBasicBlock &miBB = MachineCodeForBasicBlock::get(BI); MachineBasicBlock &miBB = MachineBasicBlock::get(BI);
writeNumber(bb); writeNumber(bb);
//Out << " BB: "<<(void *)BI<<"\n"; //Out << " BB: "<<(void *)BI<<"\n";
//for(int i=0; i<miBB.size(); ++i) //for(int i=0; i<miBB.size(); ++i)

8
lib/Target/SparcV9/SparcV9AsmPrinter.cpp
View File

@ -13,7 +13,7 @@
#include "SparcInternals.h" #include "SparcInternals.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Constants.h" #include "llvm/Constants.h"
#include "llvm/DerivedTypes.h" #include "llvm/DerivedTypes.h"
@ -469,11 +469,11 @@ SparcFunctionAsmPrinter::emitBasicBlock(const BasicBlock *BB)
toAsm << getID(BB) << ":\n"; toAsm << getID(BB) << ":\n";
// Get the vector of machine instructions corresponding to this bb. // Get the vector of machine instructions corresponding to this bb.
const MachineCodeForBasicBlock &MIs = MachineCodeForBasicBlock::get(BB); const MachineBasicBlock &MIs = MachineBasicBlock::get(BB);
MachineCodeForBasicBlock::const_iterator MII = MIs.begin(), MIE = MIs.end();
// Loop over all of the instructions in the basic block... // Loop over all of the instructions in the basic block...
for (; MII != MIE; ++MII) for (MachineBasicBlock::const_iterator MII = MIs.begin(), MIE = MIs.end();
MII != MIE; ++MII)
emitMachineInst(*MII); emitMachineInst(*MII);
toAsm << "\n"; // Seperate BB's with newlines toAsm << "\n"; // Seperate BB's with newlines
} }

42
lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
View File

@ -1,16 +1,12 @@
// $Id$ -*-c++-*- //===-- PeepholeOpts.cpp --------------------------------------------------===//
//***************************************************************************
// File:
// PeepholeOpts.h
// //
// Purpose: // Support for performing several peephole opts in one or a few passes over the
// Support for performing several peephole opts in one or a few passes // machine code of a method.
// over the machine code of a method. //
//**************************************************************************/ //===----------------------------------------------------------------------===//
#include "llvm/CodeGen/PeepholeOpts.h" #include "llvm/CodeGen/PeepholeOpts.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineInstrInfo.h" #include "llvm/Target/MachineInstrInfo.h"
@ -18,15 +14,11 @@
#include "llvm/BasicBlock.h" #include "llvm/BasicBlock.h"
#include "llvm/Pass.h" #include "llvm/Pass.h"
//********************* Internal Class Declarations ************************/
//************************* Internal Functions *****************************/ //************************* Internal Functions *****************************/
inline void inline void
DeleteInstruction(MachineCodeForBasicBlock& mvec, DeleteInstruction(MachineBasicBlock& mvec,
MachineCodeForBasicBlock::iterator& BBI, MachineBasicBlock::iterator& BBI,
const TargetMachine& target) const TargetMachine& target)
{ {
// Check if this instruction is in a delay slot of its predecessor. // Check if this instruction is in a delay slot of its predecessor.
@ -55,8 +47,8 @@ DeleteInstruction(MachineCodeForBasicBlock& mvec,
inline bool inline bool
RemoveUselessCopies(MachineCodeForBasicBlock& mvec, RemoveUselessCopies(MachineBasicBlock& mvec,
MachineCodeForBasicBlock::iterator& BBI, MachineBasicBlock::iterator& BBI,
const TargetMachine& target) const TargetMachine& target)
{ {
if (target.getOptInfo().IsUselessCopy(*BBI)) if (target.getOptInfo().IsUselessCopy(*BBI))
@ -72,8 +64,8 @@ RemoveUselessCopies(MachineCodeForBasicBlock& mvec,
class PeepholeOpts: public BasicBlockPass { class PeepholeOpts: public BasicBlockPass {
const TargetMachine &target; const TargetMachine &target;
bool visit(MachineCodeForBasicBlock& mvec, bool visit(MachineBasicBlock& mvec,
MachineCodeForBasicBlock::iterator BBI) const; MachineBasicBlock::iterator BBI) const;
public: public:
PeepholeOpts(const TargetMachine &T): target(T) { } PeepholeOpts(const TargetMachine &T): target(T) { }
bool runOnBasicBlock(BasicBlock &BB); // apply this pass to each BB bool runOnBasicBlock(BasicBlock &BB); // apply this pass to each BB
@ -90,8 +82,8 @@ X("peephole", "Peephole Optimization", createPeepholeOptsPass);
* instruction before MI, but not * instruction before MI, but not
*/ */
bool bool
PeepholeOpts::visit(MachineCodeForBasicBlock& mvec, PeepholeOpts::visit(MachineBasicBlock& mvec,
MachineCodeForBasicBlock::iterator BBI) const MachineBasicBlock::iterator BBI) const
{ {
bool changed = false; bool changed = false;
@ -108,16 +100,16 @@ bool
PeepholeOpts::runOnBasicBlock(BasicBlock &BB) PeepholeOpts::runOnBasicBlock(BasicBlock &BB)
{ {
// Get the machine instructions for this BB // Get the machine instructions for this BB
MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(&BB); MachineBasicBlock& mvec = MachineBasicBlock::get(&BB);
// Iterate over all machine instructions in the BB // Iterate over all machine instructions in the BB
// Use a reverse iterator to allow deletion of MI or any instruction after it. // Use a reverse iterator to allow deletion of MI or any instruction after it.
// Insertions or deletions *before* MI are not safe. // Insertions or deletions *before* MI are not safe.
// //
for (MachineCodeForBasicBlock::reverse_iterator RI=mvec.rbegin(), for (MachineBasicBlock::reverse_iterator RI=mvec.rbegin(),
RE=mvec.rend(); RI != RE; ) RE=mvec.rend(); RI != RE; )
{ {
MachineCodeForBasicBlock::iterator BBI = RI.base()-1; // save before incr MachineBasicBlock::iterator BBI = RI.base()-1; // save before incr
++RI; // pre-increment to delete MI or after it ++RI; // pre-increment to delete MI or after it
visit(mvec, BBI); visit(mvec, BBI);
} }

6
lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
View File

@ -12,7 +12,7 @@
#include "SparcInternals.h" #include "SparcInternals.h"
#include "SparcRegClassInfo.h" #include "SparcRegClassInfo.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineCodeForBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/InstrSelectionSupport.h" #include "llvm/CodeGen/InstrSelectionSupport.h"
@ -118,7 +118,7 @@ void InsertPrologEpilogCode::InsertPrologCode(Function &F)
mvec.push_back(M); mvec.push_back(M);
} }
MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(&F.getEntryNode()); MachineBasicBlock& bbMvec = MachineBasicBlock::get(&F.getEntryNode());
bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end()); bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end());
} }
@ -134,7 +134,7 @@ void InsertPrologEpilogCode::InsertEpilogCode(Function &F)
(int64_t)0); (int64_t)0);
Restore->SetMachineOperandReg(2, Target.getRegInfo().getZeroRegNum()); Restore->SetMachineOperandReg(2, Target.getRegInfo().getZeroRegNum());
MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(I); MachineBasicBlock& bbMvec = MachineBasicBlock::get(I);
MachineCodeForInstruction &termMvec = MachineCodeForInstruction &termMvec =
MachineCodeForInstruction::get(TermInst); MachineCodeForInstruction::get(TermInst);