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ARM isel for vld1, opcode selection for register stride post-index pseudos.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143158 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-10-27 22:25:42 +00:00
parent e39102819e
commit 55dabaa73a
1 changed files with 4 additions and 0 deletions
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4
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -1562,6 +1562,10 @@ static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
case ARM::VLD1q8PseudoWB_fixed: return ARM::VLD1q8PseudoWB_register;
case ARM::VLD1q16PseudoWB_fixed: return ARM::VLD1q16PseudoWB_register;
case ARM::VLD1q32PseudoWB_fixed: return ARM::VLD1q32PseudoWB_register;
case ARM::VLD1q64PseudoWB_fixed: return ARM::VLD1q64PseudoWB_register;
}
return Opc; // If not one we handle, return it unchanged.
}