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Add all codegen passes to the PassManager via TargetPassConfig.

Browse Source 
This is a preliminary step toward having TargetPassConfig be able to
start and stop the compilation at specified passes for unit testing
and debugging.  No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2012-07-02 19:48:31 +00:00
parent 8add7b48d2
commit 564fbf6aff
14 changed files with 113 additions and 100 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
include/llvm/CodeGen/Passes.h
View File

@ -55,9 +55,11 @@ public:
/// optimization after regalloc.
static char PostRAMachineLICMID;
private:
PassManagerBase *PM;
protected:
TargetMachine *TM;
PassManagerBase *PM;
PassConfigImpl *Impl; // Internal data structures
bool Initialized; // Flagged after all passes are configured.
@ -122,6 +124,9 @@ public:
/// transforms following machine independent optimization.
virtual void addIRPasses();
/// Add passes to lower exception handling for the code generator.
void addPassesToHandleExceptions();
/// Add common passes that perform LLVM IR to IR transforms in preparation for
/// instruction selection.
virtual void addISelPrepare();
@ -235,6 +240,9 @@ protected:
/// Return the pass that was added, or NoPassID.
AnalysisID addPass(char &ID);
/// Add a pass to the PassManager.
void addPass(Pass *P);
/// addMachinePasses helper to create the target-selected or overriden
/// regalloc pass.
FunctionPass *createRegAllocPass(bool Optimized);
@ -242,7 +250,7 @@ protected:
/// printAndVerify - Add a pass to dump then verify the machine function, if
/// those steps are enabled.
///
void printAndVerify(const char *Banner) const;
void printAndVerify(const char *Banner);
};
} // namespace llvm

30
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -78,34 +78,6 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
"and that InitializeAllTargetMCs() is being invoked!");
}
/// Turn exception handling constructs into something the code generators can
/// handle.
static void addPassesToHandleExceptions(TargetMachine *TM,
PassManagerBase &PM) {
switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
case ExceptionHandling::SjLj:
// SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
// Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
// catch info can get misplaced when a selector ends up more than one block
// removed from the parent invoke(s). This could happen when a landing
// pad is shared by multiple invokes and is also a target of a normal
// edge from elsewhere.
PM.add(createSjLjEHPreparePass(TM->getTargetLowering()));
// FALLTHROUGH
case ExceptionHandling::DwarfCFI:
case ExceptionHandling::ARM:
case ExceptionHandling::Win64:
PM.add(createDwarfEHPass(TM));
break;
case ExceptionHandling::None:
PM.add(createLowerInvokePass(TM->getTargetLowering()));
// The lower invoke pass may create unreachable code. Remove it.
PM.add(createUnreachableBlockEliminationPass());
break;
}
}
/// addPassesToX helper drives creation and initialization of TargetPassConfig.
static MCContext *addPassesToGenerateCode(LLVMTargetMachine *TM,
PassManagerBase &PM,
@ -120,7 +92,7 @@ static MCContext *addPassesToGenerateCode(LLVMTargetMachine *TM,
PassConfig->addIRPasses();
addPassesToHandleExceptions(TM, PM);
PassConfig->addPassesToHandleExceptions();
PassConfig->addISelPrepare();

73
lib/CodeGen/Passes.cpp
View File

@ -22,6 +22,7 @@
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Assembly/PrintModulePass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
@ -215,7 +216,7 @@ TargetPassConfig::~TargetPassConfig() {
// Out of line constructor provides default values for pass options and
// registers all common codegen passes.
TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
: ImmutablePass(ID), TM(tm), PM(&pm), Impl(0), Initialized(false),
: ImmutablePass(ID), PM(&pm), TM(tm), Impl(0), Initialized(false),
DisableVerify(false),
EnableTailMerge(true) {
@ -272,6 +273,11 @@ AnalysisID TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
return I->second;
}
/// Add a pass to the PassManager.
void TargetPassConfig::addPass(Pass *P) {
PM->add(P);
}
/// Add a CodeGen pass at this point in the pipeline after checking for target
/// and command line overrides.
AnalysisID TargetPassConfig::addPass(char &ID) {
@ -285,7 +291,7 @@ AnalysisID TargetPassConfig::addPass(char &ID) {
Pass *P = Pass::createPass(FinalID);
if (!P)
llvm_unreachable("Pass ID not registered");
PM->add(P);
addPass(P);
// Add the passes after the pass P if there is any.
for (SmallVector<std::pair<AnalysisID, AnalysisID>, 4>::iterator
I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
@ -294,18 +300,18 @@ AnalysisID TargetPassConfig::addPass(char &ID) {
assert((*I).second && "Illegal Pass ID!");
Pass *NP = Pass::createPass((*I).second);
assert(NP && "Pass ID not registered");
PM->add(NP);
addPass(NP);
}
}
return FinalID;
}
void TargetPassConfig::printAndVerify(const char *Banner) const {
void TargetPassConfig::printAndVerify(const char *Banner) {
if (TM->shouldPrintMachineCode())
PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
addPass(createMachineFunctionPrinterPass(dbgs(), Banner));
if (VerifyMachineCode)
PM->add(createMachineVerifierPass(Banner));
addPass(createMachineVerifierPass(Banner));
}
/// Add common target configurable passes that perform LLVM IR to IR transforms
@ -315,46 +321,73 @@ void TargetPassConfig::addIRPasses() {
// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
// BasicAliasAnalysis wins if they disagree. This is intended to help
// support "obvious" type-punning idioms.
PM->add(createTypeBasedAliasAnalysisPass());
PM->add(createBasicAliasAnalysisPass());
addPass(createTypeBasedAliasAnalysisPass());
addPass(createBasicAliasAnalysisPass());
// Before running any passes, run the verifier to determine if the input
// coming from the front-end and/or optimizer is valid.
if (!DisableVerify)
PM->add(createVerifierPass());
addPass(createVerifierPass());
// Run loop strength reduction before anything else.
if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
PM->add(createLoopStrengthReducePass(getTargetLowering()));
addPass(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR)
PM->add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
addPass(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
}
PM->add(createGCLoweringPass());
addPass(createGCLoweringPass());
// Make sure that no unreachable blocks are instruction selected.
PM->add(createUnreachableBlockEliminationPass());
addPass(createUnreachableBlockEliminationPass());
}
/// Turn exception handling constructs into something the code generators can
/// handle.
void TargetPassConfig::addPassesToHandleExceptions() {
switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
case ExceptionHandling::SjLj:
// SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
// Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
// catch info can get misplaced when a selector ends up more than one block
// removed from the parent invoke(s). This could happen when a landing
// pad is shared by multiple invokes and is also a target of a normal
// edge from elsewhere.
addPass(createSjLjEHPreparePass(TM->getTargetLowering()));
// FALLTHROUGH
case ExceptionHandling::DwarfCFI:
case ExceptionHandling::ARM:
case ExceptionHandling::Win64:
addPass(createDwarfEHPass(TM));
break;
case ExceptionHandling::None:
addPass(createLowerInvokePass(TM->getTargetLowering()));
// The lower invoke pass may create unreachable code. Remove it.
addPass(createUnreachableBlockEliminationPass());
break;
}
}
/// Add common passes that perform LLVM IR to IR transforms in preparation for
/// instruction selection.
void TargetPassConfig::addISelPrepare() {
if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
PM->add(createCodeGenPreparePass(getTargetLowering()));
addPass(createCodeGenPreparePass(getTargetLowering()));
PM->add(createStackProtectorPass(getTargetLowering()));
addPass(createStackProtectorPass(getTargetLowering()));
addPreISel();
if (PrintISelInput)
PM->add(createPrintFunctionPass("\n\n"
addPass(createPrintFunctionPass("\n\n"
"*** Final LLVM Code input to ISel ***\n",
&dbgs()));
// All passes which modify the LLVM IR are now complete; run the verifier
// to ensure that the IR is valid.
if (!DisableVerify)
PM->add(createVerifierPass());
addPass(createVerifierPass());
}
/// Add the complete set of target-independent postISel code generator passes.
@ -447,7 +480,7 @@ void TargetPassConfig::addMachinePasses() {
// GC
addPass(GCMachineCodeAnalysisID);
if (PrintGCInfo)
PM->add(createGCInfoPrinter(dbgs()));
addPass(createGCInfoPrinter(dbgs()));
// Basic block placement.
if (getOptLevel() != CodeGenOpt::None)
@ -564,7 +597,7 @@ void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
addPass(PHIEliminationID);
addPass(TwoAddressInstructionPassID);
PM->add(RegAllocPass);
addPass(RegAllocPass);
printAndVerify("After Register Allocation");
}
@ -602,7 +635,7 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
printAndVerify("After Machine Scheduling");
// Add the selected register allocation pass.
PM->add(RegAllocPass);
addPass(RegAllocPass);
printAndVerify("After Register Allocation, before rewriter");
// Allow targets to change the register assignments before rewriting.

20
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -136,22 +136,22 @@ TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
bool ARMPassConfig::addPreISel() {
if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
PM->add(createGlobalMergePass(TM->getTargetLowering()));
addPass(createGlobalMergePass(TM->getTargetLowering()));
return false;
}
bool ARMPassConfig::addInstSelector() {
PM->add(createARMISelDag(getARMTargetMachine(), getOptLevel()));
addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
return false;
}
bool ARMPassConfig::addPreRegAlloc() {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
PM->add(createARMLoadStoreOptimizationPass(true));
addPass(createARMLoadStoreOptimizationPass(true));
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
PM->add(createMLxExpansionPass());
addPass(createMLxExpansionPass());
return true;
}
@ -159,23 +159,23 @@ bool ARMPassConfig::addPreSched2() {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only()) {
PM->add(createARMLoadStoreOptimizationPass());
addPass(createARMLoadStoreOptimizationPass());
printAndVerify("After ARM load / store optimizer");
}
if (getARMSubtarget().hasNEON())
PM->add(createExecutionDependencyFixPass(&ARM::DPRRegClass));
addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
}
// Expand some pseudo instructions into multiple instructions to allow
// proper scheduling.
PM->add(createARMExpandPseudoPass());
addPass(createARMExpandPseudoPass());
if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only())
addPass(IfConverterID);
}
if (getARMSubtarget().isThumb2())
PM->add(createThumb2ITBlockPass());
addPass(createThumb2ITBlockPass());
return true;
}
@ -183,13 +183,13 @@ bool ARMPassConfig::addPreSched2() {
bool ARMPassConfig::addPreEmitPass() {
if (getARMSubtarget().isThumb2()) {
if (!getARMSubtarget().prefers32BitThumb())
PM->add(createThumb2SizeReductionPass());
addPass(createThumb2SizeReductionPass());
// Constant island pass work on unbundled instructions.
addPass(UnpackMachineBundlesID);
}
PM->add(createARMConstantIslandPass());
addPass(createARMConstantIslandPass());
return true;
}

6
lib/Target/CellSPU/SPUTargetMachine.cpp
View File

@ -72,7 +72,7 @@ TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM) {
bool SPUPassConfig::addInstSelector() {
// Install an instruction selector.
PM->add(createSPUISelDag(getSPUTargetMachine()));
addPass(createSPUISelDag(getSPUTargetMachine()));
return false;
}
@ -85,9 +85,9 @@ bool SPUPassConfig::addPreEmitPass() {
(BuilderFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol(
"createTCESchedulerPass");
if (schedulerCreator != NULL)
PM->add(schedulerCreator("cellspu"));
addPass(schedulerCreator("cellspu"));
//align instructions with nops/lnops for dual issue
PM->add(createSPUNopFillerPass(getSPUTargetMachine()));
addPass(createSPUNopFillerPass(getSPUTargetMachine()));
return true;
}

20
lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -102,22 +102,22 @@ TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
}
bool HexagonPassConfig::addInstSelector() {
PM->add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
PM->add(createHexagonISelDag(getHexagonTargetMachine()));
PM->add(createHexagonPeephole());
addPass(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
addPass(createHexagonISelDag(getHexagonTargetMachine()));
addPass(createHexagonPeephole());
return false;
}
bool HexagonPassConfig::addPreRegAlloc() {
if (!DisableHardwareLoops) {
PM->add(createHexagonHardwareLoops());
addPass(createHexagonHardwareLoops());
}
return false;
}
bool HexagonPassConfig::addPostRegAlloc() {
PM->add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
addPass(createHexagonCFGOptimizer(getHexagonTargetMachine()));
return true;
}
@ -130,19 +130,19 @@ bool HexagonPassConfig::addPreSched2() {
bool HexagonPassConfig::addPreEmitPass() {
if (!DisableHardwareLoops) {
PM->add(createHexagonFixupHwLoops());
addPass(createHexagonFixupHwLoops());
}
PM->add(createHexagonNewValueJump());
addPass(createHexagonNewValueJump());
// Expand Spill code for predicate registers.
PM->add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
addPass(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
// Split up TFRcondsets into conditional transfers.
PM->add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
addPass(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
// Create Packets.
PM->add(createHexagonPacketizer());
addPass(createHexagonPacketizer());
return false;
}

4
lib/Target/MBlaze/MBlazeTargetMachine.cpp
View File

@ -68,7 +68,7 @@ TargetPassConfig *MBlazeTargetMachine::createPassConfig(PassManagerBase &PM) {
// Install an instruction selector pass using
// the ISelDag to gen MBlaze code.
bool MBlazePassConfig::addInstSelector() {
PM->add(createMBlazeISelDag(getMBlazeTargetMachine()));
addPass(createMBlazeISelDag(getMBlazeTargetMachine()));
return false;
}
@ -76,6 +76,6 @@ bool MBlazePassConfig::addInstSelector() {
// machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes.
bool MBlazePassConfig::addPreEmitPass() {
PM->add(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
addPass(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
return true;
}

4
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -60,12 +60,12 @@ TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM) {
bool MSP430PassConfig::addInstSelector() {
// Install an instruction selector.
PM->add(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
return false;
}
bool MSP430PassConfig::addPreEmitPass() {
// Must run branch selection immediately preceding the asm printer.
PM->add(createMSP430BranchSelectionPass());
addPass(createMSP430BranchSelectionPass());
return false;
}

6
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -116,7 +116,7 @@ TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
// Install an instruction selector pass using
// the ISelDag to gen Mips code.
bool MipsPassConfig::addInstSelector() {
PM->add(createMipsISelDag(getMipsTargetMachine()));
addPass(createMipsISelDag(getMipsTargetMachine()));
return false;
}
@ -125,11 +125,11 @@ bool MipsPassConfig::addInstSelector() {
// print out the code after the passes.
bool MipsPassConfig::addPreEmitPass() {
MipsTargetMachine &TM = getMipsTargetMachine();
PM->add(createMipsDelaySlotFillerPass(TM));
addPass(createMipsDelaySlotFillerPass(TM));
// NOTE: long branch has not been implemented for mips16.
if (TM.getSubtarget<MipsSubtarget>().hasStandardEncoding())
PM->add(createMipsLongBranchPass(TM));
addPass(createMipsLongBranchPass(TM));
return true;
}

10
lib/Target/NVPTX/NVPTXTargetMachine.cpp
View File

@ -120,11 +120,11 @@ TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
}
bool NVPTXPassConfig::addInstSelector() {
PM->add(createLowerAggrCopies());
PM->add(createSplitBBatBarPass());
PM->add(createAllocaHoisting());
PM->add(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
PM->add(createVectorElementizePass(getNVPTXTargetMachine()));
addPass(createLowerAggrCopies());
addPass(createSplitBBatBarPass());
addPass(createAllocaHoisting());
addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
addPass(createVectorElementizePass(getNVPTXTargetMachine()));
return false;
}

6
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -98,20 +98,20 @@ TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
bool PPCPassConfig::addPreRegAlloc() {
if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
PM->add(createPPCCTRLoops());
addPass(createPPCCTRLoops());
return false;
}
bool PPCPassConfig::addInstSelector() {
// Install an instruction selector.
PM->add(createPPCISelDag(getPPCTargetMachine()));
addPass(createPPCISelDag(getPPCTargetMachine()));
return false;
}
bool PPCPassConfig::addPreEmitPass() {
// Must run branch selection immediately preceding the asm printer.
PM->add(createPPCBranchSelectionPass());
addPass(createPPCBranchSelectionPass());
return false;
}

6
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -60,7 +60,7 @@ TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
}
bool SparcPassConfig::addInstSelector() {
PM->add(createSparcISelDag(getSparcTargetMachine()));
addPass(createSparcISelDag(getSparcTargetMachine()));
return false;
}
@ -68,8 +68,8 @@ bool SparcPassConfig::addInstSelector() {
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
bool SparcPassConfig::addPreEmitPass(){
PM->add(createSparcFPMoverPass(getSparcTargetMachine()));
PM->add(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
addPass(createSparcFPMoverPass(getSparcTargetMachine()));
addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
return true;
}

14
lib/Target/X86/X86TargetMachine.cpp
View File

@ -145,38 +145,38 @@ TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
bool X86PassConfig::addInstSelector() {
// Install an instruction selector.
PM->add(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
// For ELF, cleanup any local-dynamic TLS accesses.
if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
PM->add(createCleanupLocalDynamicTLSPass());
addPass(createCleanupLocalDynamicTLSPass());
// For 32-bit, prepend instructions to set the "global base reg" for PIC.
if (!getX86Subtarget().is64Bit())
PM->add(createGlobalBaseRegPass());
addPass(createGlobalBaseRegPass());
return false;
}
bool X86PassConfig::addPreRegAlloc() {
PM->add(createX86MaxStackAlignmentHeuristicPass());
addPass(createX86MaxStackAlignmentHeuristicPass());
return false; // -print-machineinstr shouldn't print after this.
}
bool X86PassConfig::addPostRegAlloc() {
PM->add(createX86FloatingPointStackifierPass());
addPass(createX86FloatingPointStackifierPass());
return true; // -print-machineinstr should print after this.
}
bool X86PassConfig::addPreEmitPass() {
bool ShouldPrint = false;
if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
PM->add(createExecutionDependencyFixPass(&X86::VR128RegClass));
addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
ShouldPrint = true;
}
if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
PM->add(createX86IssueVZeroUpperPass());
addPass(createX86IssueVZeroUpperPass());
ShouldPrint = true;
}

2
lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -55,7 +55,7 @@ TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
}
bool XCorePassConfig::addInstSelector() {
PM->add(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
addPass(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
return false;
}