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Added virtual function to generate an instruction sequence to

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load a constant into a register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@862 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve 2001-10-18 00:02:06 +00:00
parent 30764b8366
commit 5684c4e2b4
3 changed files with 53 additions and 4 deletions
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20
include/llvm/Target/MachineInstrInfo.h
View File

@ -9,8 +9,13 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/DataTypes.h"
#include <vector>
class MachineInstrDescriptor;
class TmpInstruction;
class MachineInstr;
class Value;
class Instruction;
typedef int InstrSchedClass;
@ -211,6 +216,21 @@ public:
isSignExtended = getDescriptor(opCode).immedIsSignExtended;
return getDescriptor(opCode).maxImmedConst;
}
//-------------------------------------------------------------------------
// Code generation support for creating individual machine instructions
//-------------------------------------------------------------------------
// Create an instruction sequence to put the constant `val' into
// the virtual register `dest'. `val' may be a ConstPoolVal or a
// GlobalValue, viz., the constant address of a global variable or function.
// The generated instructions are returned in `minstrVec'.
// Any temp. registers (TmpInstruction) created are returned in `tempVec'.
//
virtual void CreateCodeToLoadConst(Value* val,
Instruction* dest,
vector<MachineInstr*>& minstrVec,
vector<TmpInstruction*>& temps) const =0;
};
#endif

20
include/llvm/Target/TargetInstrInfo.h
View File

@ -9,8 +9,13 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/DataTypes.h"
#include <vector>
class MachineInstrDescriptor;
class TmpInstruction;
class MachineInstr;
class Value;
class Instruction;
typedef int InstrSchedClass;
@ -211,6 +216,21 @@ public:
isSignExtended = getDescriptor(opCode).immedIsSignExtended;
return getDescriptor(opCode).maxImmedConst;
}
//-------------------------------------------------------------------------
// Code generation support for creating individual machine instructions
//-------------------------------------------------------------------------
// Create an instruction sequence to put the constant `val' into
// the virtual register `dest'. `val' may be a ConstPoolVal or a
// GlobalValue, viz., the constant address of a global variable or function.
// The generated instructions are returned in `minstrVec'.
// Any temp. registers (TmpInstruction) created are returned in `tempVec'.
//
virtual void CreateCodeToLoadConst(Value* val,
Instruction* dest,
vector<MachineInstr*>& minstrVec,
vector<TmpInstruction*>& temps) const =0;
};
#endif

17
lib/Target/SparcV9/SparcV9Internals.h
View File

@ -85,7 +85,7 @@ class UltraSparcInstrInfo : public MachineInstrInfo {
public:
/*ctor*/ UltraSparcInstrInfo();
virtual bool hasResultInterlock (MachineOpCode opCode)
virtual bool hasResultInterlock (MachineOpCode opCode) const
{
// All UltraSPARC instructions have interlocks (note that delay slots
// are not considered here).
@ -96,10 +96,19 @@ public:
return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
}
//-------------------------------------------------------------------------
// Code generation support for creating individual machine instructions
//-------------------------------------------------------------------------
// Create an instruction sequence to put the constant `val' into
// the virtual register `dest'. The generated instructions are
// returned in `minstrVec'. Any temporary registers (TmpInstruction)
// created are returned in `tempVec'.
//
virtual void CreateCodeToLoadConst(Value* val,
Instruction* dest,
vector<MachineInstr*>& minstrVec,
vector<TmpInstruction*>& tempVec) const;
};