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ARM assembly parsing and encoding for SSAT instruction.

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Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-07-25 22:20:28 +00:00
parent 478849e98c
commit 580f4a9c1c
8 changed files with 179 additions and 63 deletions
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12
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -1732,17 +1732,11 @@ static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
decodeRm(insn))));
if (NumOpsAdded == 4) {
ARM_AM::ShiftOpc Opc = (slice(insn, 6, 6) != 0 ? ARM_AM::asr : ARM_AM::lsl);
// Inst{6} encodes the shift type.
bool isASR = slice(insn, 6, 6);
// Inst{11-7} encodes the imm5 shift amount.
unsigned ShAmt = slice(insn, 11, 7);
if (ShAmt == 0) {
// A8.6.183. Possible ASR shift amount of 32...
if (Opc == ARM_AM::asr)
ShAmt = 32;
else
Opc = ARM_AM::no_shift;
}
MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt)));
MI.addOperand(MCOperand::CreateImm(isASR << 5 | ShAmt));
}
return true;
}