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remove "Slot", it is dead

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26609 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-08 04:37:58 +00:00
parent b0d21ef20c
commit 5874f82564
2 changed files with 56 additions and 34 deletions
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25
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -1798,7 +1798,30 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
break; break;
case TargetLowering::Legal: break; case TargetLowering::Legal: break;
case TargetLowering::Expand: case TargetLowering::Expand:
// Floating point mod -> fmod libcall. // If this target supports fabs/fneg natively, do this efficiently.
if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
// Get the sign bit of the RHS.
MVT::ValueType IVT =
Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
// Get the absolute value of the result.
SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
// Select between the nabs and abs value based on the sign bit of
// the input.
Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
AbsVal),
AbsVal);
Result = LegalizeOp(Result);
break;
}
// Otherwise, do bitwise ops!
// copysign -> copysignf/copysign libcall.
const char *FnName; const char *FnName;
if (Node->getValueType(0) == MVT::f32) { if (Node->getValueType(0) == MVT::f32) {
FnName = "copysignf"; FnName = "copysignf";

13
lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
View File

@ -20,7 +20,6 @@
#define DEBUG_TYPE "sched" #define DEBUG_TYPE "sched"
#include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
@ -54,7 +53,6 @@ struct SUnit {
bool isDefNUseOperand; // Is a def&use operand. bool isDefNUseOperand; // Is a def&use operand.
unsigned Latency; // Node latency. unsigned Latency; // Node latency.
unsigned CycleBound; // Upper/lower cycle to be scheduled at. unsigned CycleBound; // Upper/lower cycle to be scheduled at.
unsigned Slot; // Cycle node is scheduled at.
SUnit *Next; SUnit *Next;
SUnit(SDNode *node) SUnit(SDNode *node)
@ -62,10 +60,11 @@ struct SUnit {
NumChainPredsLeft(0), NumChainSuccsLeft(0), NumChainPredsLeft(0), NumChainSuccsLeft(0),
SethiUllman(INT_MIN), SethiUllman(INT_MIN),
isTwoAddress(false), isDefNUseOperand(false), isTwoAddress(false), isDefNUseOperand(false),
Latency(0), CycleBound(0), Slot(0), Next(NULL) {} Latency(0), CycleBound(0), Next(NULL) {}
void dump(const SelectionDAG *G, bool All=true) const; void dump(const SelectionDAG *G, bool All=true) const;
}; };
}
void SUnit::dump(const SelectionDAG *G, bool All) const { void SUnit::dump(const SelectionDAG *G, bool All) const {
std::cerr << "SU: "; std::cerr << "SU: ";
@ -122,6 +121,7 @@ void SUnit::dump(const SelectionDAG *G, bool All) const {
} }
} }
namespace {
/// Sorting functions for the Available queue. /// Sorting functions for the Available queue.
struct ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> { struct ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
bool operator()(const SUnit* left, const SUnit* right) const { bool operator()(const SUnit* left, const SUnit* right) const {
@ -159,8 +159,10 @@ struct ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
return false; return false;
} }
}; };
} // end anonymous namespace
namespace {
/// ScheduleDAGList - List scheduler. /// ScheduleDAGList - List scheduler.
class ScheduleDAGList : public ScheduleDAG { class ScheduleDAGList : public ScheduleDAG {
private: private:
@ -219,7 +221,7 @@ private:
void BuildSchedUnits(); void BuildSchedUnits();
void EmitSchedule(); void EmitSchedule();
}; };
} // end namespace } // end anonymous namespace
HazardRecognizer::~HazardRecognizer() {} HazardRecognizer::~HazardRecognizer() {}
@ -305,7 +307,6 @@ void ScheduleDAGList::ScheduleNodeBottomUp(AvailableQueueTy &Available,
DEBUG(SU->dump(&DAG, false)); DEBUG(SU->dump(&DAG, false));
Sequence.push_back(SU); Sequence.push_back(SU);
SU->Slot = CurrCycle;
// Bottom up: release predecessors // Bottom up: release predecessors
for (std::set<SUnit*>::iterator I1 = SU->Preds.begin(), for (std::set<SUnit*>::iterator I1 = SU->Preds.begin(),
@ -329,7 +330,6 @@ void ScheduleDAGList::ScheduleNodeTopDown(AvailableQueueTy &Available,
DEBUG(SU->dump(&DAG, false)); DEBUG(SU->dump(&DAG, false));
Sequence.push_back(SU); Sequence.push_back(SU);
SU->Slot = CurrCycle;
// Bottom up: release successors. // Bottom up: release successors.
for (std::set<SUnit*>::iterator I1 = SU->Succs.begin(), for (std::set<SUnit*>::iterator I1 = SU->Succs.begin(),
@ -384,7 +384,6 @@ void ScheduleDAGList::ListScheduleBottomUp() {
// Add entry node last // Add entry node last
if (DAG.getEntryNode().Val != DAG.getRoot().Val) { if (DAG.getEntryNode().Val != DAG.getRoot().Val) {
SUnit *Entry = SUnitMap[DAG.getEntryNode().Val]; SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
Entry->Slot = CurrCycle;
Sequence.push_back(Entry); Sequence.push_back(Entry);
} }