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Change MachineInstrBuilder::addReg() to take a flag instead of a list of

Browse Source 
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2009-05-13 21:33:08 +00:00
parent 556d0a0d15
commit 587daedce2
21 changed files with 242 additions and 165 deletions
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2
docs/CodeGenerator.html
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@ -600,7 +600,7 @@ BuildMI(MBB, X86::JNE, 1).addMBB(&MBB);
<div class="doc_code"> <div class="doc_code">
<pre> <pre>
MI.addReg(Reg, MachineOperand::Def); MI.addReg(Reg, RegState::Define);
</pre> </pre>
</div> </div>

56
include/llvm/CodeGen/MachineInstrBuilder.h
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@ -23,6 +23,18 @@ namespace llvm {
class TargetInstrDesc; class TargetInstrDesc;
namespace RegState {
enum {
Define = 0x2,
Implicit = 0x4,
Kill = 0x8,
Dead = 0x10,
EarlyClobber = 0x20,
ImplicitDefine = Implicit | Define,
ImplicitKill = Implicit | Kill
};
}
class MachineInstrBuilder { class MachineInstrBuilder {
MachineInstr *MI; MachineInstr *MI;
public: public:
@ -36,12 +48,17 @@ public:
/// addReg - Add a new virtual register operand... /// addReg - Add a new virtual register operand...
/// ///
const const
MachineInstrBuilder &addReg(unsigned RegNo, bool isDef = false, MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
bool isImp = false, bool isKill = false, unsigned SubReg = 0) const {
bool isDead = false, unsigned SubReg = 0, assert((flags & 0x1) == 0 &&
bool isEarlyClobber = false) const { "Passing in 'true' to addReg is forbidden! Use enums instead.");
MI->addOperand(MachineOperand::CreateReg(RegNo, isDef, isImp, isKill, MI->addOperand(MachineOperand::CreateReg(RegNo,
isDead, SubReg, isEarlyClobber)); flags & RegState::Define,
flags & RegState::Implicit,
flags & RegState::Kill,
flags & RegState::Dead,
SubReg,
flags & RegState::EarlyClobber));
return *this; return *this;
} }
@ -97,9 +114,13 @@ public:
const MachineInstrBuilder &addOperand(const MachineOperand &MO) const { const MachineInstrBuilder &addOperand(const MachineOperand &MO) const {
if (MO.isReg()) if (MO.isReg())
return addReg(MO.getReg(), MO.isDef(), MO.isImplicit(), return addReg(MO.getReg(),
MO.isKill(), MO.isDead(), MO.getSubReg(), (MO.isDef() ? RegState::Define : 0) |
MO.isEarlyClobber()); (MO.isImplicit() ? RegState::Implicit : 0) |
(MO.isKill() ? RegState::Kill : 0) |
(MO.isDead() ? RegState::Dead : 0) |
(MO.isEarlyClobber() ? RegState::EarlyClobber : 0),
MO.getSubReg());
if (MO.isImm()) if (MO.isImm())
return addImm(MO.getImm()); return addImm(MO.getImm());
if (MO.isFI()) if (MO.isFI())
@ -135,7 +156,7 @@ inline MachineInstrBuilder BuildMI(MachineFunction &MF,
const TargetInstrDesc &TID, const TargetInstrDesc &TID,
unsigned DestReg) { unsigned DestReg) {
return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL)) return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL))
.addReg(DestReg, true); .addReg(DestReg, RegState::Define);
} }
/// BuildMI - This version of the builder inserts the newly-built /// BuildMI - This version of the builder inserts the newly-built
@ -149,7 +170,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
unsigned DestReg) { unsigned DestReg) {
MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL); MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL);
BB.insert(I, MI); BB.insert(I, MI);
return MachineInstrBuilder(MI).addReg(DestReg, true); return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
} }
/// BuildMI - This version of the builder inserts the newly-built /// BuildMI - This version of the builder inserts the newly-built
@ -186,6 +207,19 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
return BuildMI(*BB, BB->end(), DL, TID, DestReg); return BuildMI(*BB, BB->end(), DL, TID, DestReg);
} }
inline unsigned getDefRegState(bool B) {
return B ? RegState::Define : 0;
}
inline unsigned getImplRegState(bool B) {
return B ? RegState::Implicit : 0;
}
inline unsigned getKillRegState(bool B) {
return B ? RegState::Kill : 0;
}
inline unsigned getDeadRegState(bool B) {
return B ? RegState::Dead : 0;
}
} // End llvm namespace } // End llvm namespace
#endif #endif

6
lib/CodeGen/TargetInstrInfoImpl.cpp
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@ -45,9 +45,9 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
bool Reg0IsDead = MI->getOperand(0).isDead(); bool Reg0IsDead = MI->getOperand(0).isDead();
MachineFunction &MF = *MI->getParent()->getParent(); MachineFunction &MF = *MI->getParent()->getParent();
return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
.addReg(Reg0, true, false, false, Reg0IsDead) .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
.addReg(Reg2, false, false, Reg2IsKill) .addReg(Reg2, getKillRegState(Reg2IsKill))
.addReg(Reg1, false, false, Reg1IsKill); .addReg(Reg1, getKillRegState(Reg2IsKill));
} }
if (ChangeReg0) if (ChangeReg0)

26
lib/Target/ARM/ARMInstrInfo.cpp
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@ -546,23 +546,23 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
assert (!AFI->isThumbFunction()); assert (!AFI->isThumbFunction());
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addReg(0).addImm(0)); .addFrameIndex(FI).addReg(0).addImm(0));
} else if (RC == ARM::tGPRRegisterClass) { } else if (RC == ARM::tGPRRegisterClass) {
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
assert (AFI->isThumbFunction()); assert (AFI->isThumbFunction());
BuildMI(MBB, I, DL, get(ARM::tSpill)) BuildMI(MBB, I, DL, get(ARM::tSpill))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0); .addFrameIndex(FI).addImm(0);
} else if (RC == ARM::DPRRegisterClass) { } else if (RC == ARM::DPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0)); .addFrameIndex(FI).addImm(0));
} else { } else {
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS)) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0)); .addFrameIndex(FI).addImm(0));
} }
} }
@ -579,7 +579,7 @@ void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
if (AFI->isThumbFunction()) { if (AFI->isThumbFunction()) {
Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR; Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
MachineInstrBuilder MIB = MachineInstrBuilder MIB =
BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
for (unsigned i = 0, e = Addr.size(); i != e; ++i) for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]); MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB); NewMIs.push_back(MIB);
@ -594,7 +594,7 @@ void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
} }
MachineInstrBuilder MIB = MachineInstrBuilder MIB =
BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
for (unsigned i = 0, e = Addr.size(); i != e; ++i) for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]); MIB.addOperand(Addr[i]);
AddDefaultPred(MIB); AddDefaultPred(MIB);
@ -681,7 +681,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
unsigned Reg = CSI[i-1].getReg(); unsigned Reg = CSI[i-1].getReg();
// Add the callee-saved register as live-in. It's killed at the spill. // Add the callee-saved register as live-in. It's killed at the spill.
MBB.addLiveIn(Reg); MBB.addLiveIn(Reg);
MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); MIB.addReg(Reg, RegState::Kill);
} }
return true; return true;
} }
@ -733,13 +733,13 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
unsigned SrcReg = MI->getOperand(1).getReg(); unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill(); bool isKill = MI->getOperand(1).isKill();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load } else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg(); unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead(); bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
.addReg(DstReg, true, false, false, isDead) .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
} }
break; break;
@ -755,7 +755,7 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
// tSpill cannot take a high register operand. // tSpill cannot take a high register operand.
break; break;
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0); .addFrameIndex(FI).addImm(0);
} else { // move -> load } else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg(); unsigned DstReg = MI->getOperand(0).getReg();
@ -764,7 +764,7 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
break; break;
bool isDead = MI->getOperand(0).isDead(); bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
.addReg(DstReg, true, false, false, isDead) .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addFrameIndex(FI).addImm(0); .addFrameIndex(FI).addImm(0);
} }
break; break;
@ -792,13 +792,13 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
unsigned SrcReg = MI->getOperand(1).getReg(); unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill(); bool isKill = MI->getOperand(1).isKill();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load } else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg(); unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead(); bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
.addReg(DstReg, true, false, false, isDead) .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
} }
break; break;

19
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -159,7 +159,7 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
return false; // Probably not worth it then. return false; // Probably not worth it then.
BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase) BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase)
.addReg(Base, false, false, BaseKill).addImm(ImmedOffset) .addReg(Base, getKillRegState(BaseKill)).addImm(ImmedOffset)
.addImm(Pred).addReg(PredReg).addReg(0); .addImm(Pred).addReg(PredReg).addReg(0);
Base = NewBase; Base = NewBase;
BaseKill = true; // New base is always killed right its use. BaseKill = true; // New base is always killed right its use.
@ -170,14 +170,15 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
Opcode = getLoadStoreMultipleOpcode(Opcode); Opcode = getLoadStoreMultipleOpcode(Opcode);
MachineInstrBuilder MIB = (isAM4) MachineInstrBuilder MIB = (isAM4)
? BuildMI(MBB, MBBI, dl, TII->get(Opcode)) ? BuildMI(MBB, MBBI, dl, TII->get(Opcode))
.addReg(Base, false, false, BaseKill) .addReg(Base, getKillRegState(BaseKill))
.addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg) .addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg)
: BuildMI(MBB, MBBI, dl, TII->get(Opcode)) : BuildMI(MBB, MBBI, dl, TII->get(Opcode))
.addReg(Base, false, false, BaseKill) .addReg(Base, getKillRegState(BaseKill))
.addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs)) .addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs))
.addImm(Pred).addReg(PredReg); .addImm(Pred).addReg(PredReg);
for (unsigned i = 0; i != NumRegs; ++i) for (unsigned i = 0; i != NumRegs; ++i)
MIB = MIB.addReg(Regs[i].first, isDef, false, Regs[i].second); MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
| getKillRegState(Regs[i].second));
return true; return true;
} }
@ -516,26 +517,26 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
if (isAM2) if (isAM2)
// LDR_PRE, LDR_POST; // LDR_PRE, LDR_POST;
BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
.addReg(Base, true) .addReg(Base, RegState::Define)
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
else else
// FLDMS, FLDMD // FLDMS, FLDMD
BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
.addReg(Base, false, false, BaseKill) .addReg(Base, getKillRegState(BaseKill))
.addImm(Offset).addImm(Pred).addReg(PredReg) .addImm(Offset).addImm(Pred).addReg(PredReg)
.addReg(MI->getOperand(0).getReg(), true); .addReg(MI->getOperand(0).getReg(), RegState::Define);
} else { } else {
MachineOperand &MO = MI->getOperand(0); MachineOperand &MO = MI->getOperand(0);
if (isAM2) if (isAM2)
// STR_PRE, STR_POST; // STR_PRE, STR_POST;
BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base) BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
.addReg(MO.getReg(), false, false, MO.isKill()) .addReg(MO.getReg(), getKillRegState(BaseKill))
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
else else
// FSTMS, FSTMD // FSTMS, FSTMD
BuildMI(MBB, MBBI, dl, TII->get(NewOpc)).addReg(Base).addImm(Offset) BuildMI(MBB, MBBI, dl, TII->get(NewOpc)).addReg(Base).addImm(Offset)
.addImm(Pred).addReg(PredReg) .addImm(Pred).addReg(PredReg)
.addReg(MO.getReg(), false, false, MO.isKill()); .addReg(MO.getReg(), getKillRegState(MO.isKill()));
} }
MBB.erase(MBBI); MBB.erase(MBBI);

30
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -368,7 +368,7 @@ void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
// Build the new ADD / SUB. // Build the new ADD / SUB.
BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
.addReg(BaseReg, false, false, true).addImm(SOImmVal) .addReg(BaseReg, RegState::Kill).addImm(SOImmVal)
.addImm((unsigned)Pred).addReg(PredReg).addReg(0); .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
BaseReg = DestReg; BaseReg = DestReg;
} }
@ -426,7 +426,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
assert(BaseReg == ARM::SP && "Unexpected!"); assert(BaseReg == ARM::SP && "Unexpected!");
LdReg = ARM::R3; LdReg = ARM::R3;
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12) BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
.addReg(ARM::R3, false, false, true); .addReg(ARM::R3, RegState::Kill);
} }
if (NumBytes <= 255 && NumBytes >= 0) if (NumBytes <= 255 && NumBytes >= 0)
@ -434,7 +434,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
else if (NumBytes < 0 && NumBytes >= -255) { else if (NumBytes < 0 && NumBytes >= -255) {
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg) BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
.addReg(LdReg, false, false, true); .addReg(LdReg, RegState::Kill);
} else } else
MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, &TII, MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, &TII,
true, dl); true, dl);
@ -444,12 +444,12 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl,
TII.get(Opc), DestReg); TII.get(Opc), DestReg);
if (DestReg == ARM::SP || isSub) if (DestReg == ARM::SP || isSub)
MIB.addReg(BaseReg).addReg(LdReg, false, false, true); MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
else else
MIB.addReg(LdReg).addReg(BaseReg, false, false, true); MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
if (DestReg == ARM::SP) if (DestReg == ARM::SP)
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3) BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
.addReg(ARM::R12, false, false, true); .addReg(ARM::R12, RegState::Kill);
} }
/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
@ -518,10 +518,10 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
Bytes -= ThisVal; Bytes -= ThisVal;
BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
.addReg(BaseReg, false, false, true).addImm(ThisVal); .addReg(BaseReg, RegState::Kill).addImm(ThisVal);
} else { } else {
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
.addReg(BaseReg, false, false, true); .addReg(BaseReg, RegState::Kill);
} }
BaseReg = DestReg; BaseReg = DestReg;
} }
@ -538,7 +538,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
else { else {
bool isKill = BaseReg != ARM::SP; bool isKill = BaseReg != ARM::SP;
BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
.addReg(BaseReg, false, false, isKill).addImm(ThisVal); .addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
BaseReg = DestReg; BaseReg = DestReg;
if (Opc == ARM::tADDrSPi) { if (Opc == ARM::tADDrSPi) {
@ -556,7 +556,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
if (ExtraOpc) if (ExtraOpc)
BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg) BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg)
.addReg(DestReg, false, false, true) .addReg(DestReg, RegState::Kill)
.addImm(((unsigned)NumBytes) & 3); .addImm(((unsigned)NumBytes) & 3);
} }
@ -631,7 +631,7 @@ static void emitThumbConstant(MachineBasicBlock &MBB,
emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl); emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
if (isSub) if (isSub)
BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg) BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg)
.addReg(DestReg, false, false, true); .addReg(DestReg, RegState::Kill);
} }
/// findScratchRegister - Find a 'free' ARM register. If register scavenger /// findScratchRegister - Find a 'free' ARM register. If register scavenger
@ -918,12 +918,12 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
bool UseRR = false; bool UseRR = false;
if (ValReg == ARM::R3) { if (ValReg == ARM::R3) {
BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12) BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
.addReg(ARM::R2, false, false, true); .addReg(ARM::R2, RegState::Kill);
TmpReg = ARM::R2; TmpReg = ARM::R2;
} }
if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12) BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
.addReg(ARM::R3, false, false, true); .addReg(ARM::R3, RegState::Kill);
if (Opcode == ARM::tSpill) { if (Opcode == ARM::tSpill) {
if (FrameReg == ARM::SP) if (FrameReg == ARM::SP)
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
@ -946,10 +946,10 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MachineBasicBlock::iterator NII = next(II); MachineBasicBlock::iterator NII = next(II);
if (ValReg == ARM::R3) if (ValReg == ARM::R3)
BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2) BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2)
.addReg(ARM::R12, false, false, true); .addReg(ARM::R12, RegState::Kill);
if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3) BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
.addReg(ARM::R12, false, false, true); .addReg(ARM::R12, RegState::Kill);
} else } else
assert(false && "Unexpected opcode!"); assert(false && "Unexpected opcode!");
} else { } else {

12
lib/Target/Alpha/AlphaInstrInfo.cpp
View File

@ -187,15 +187,15 @@ AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (RC == Alpha::F4RCRegisterClass) if (RC == Alpha::F4RCRegisterClass)
BuildMI(MBB, MI, DL, get(Alpha::STS)) BuildMI(MBB, MI, DL, get(Alpha::STS))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FrameIdx).addReg(Alpha::F31); .addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass) else if (RC == Alpha::F8RCRegisterClass)
BuildMI(MBB, MI, DL, get(Alpha::STT)) BuildMI(MBB, MI, DL, get(Alpha::STT))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FrameIdx).addReg(Alpha::F31); .addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::GPRCRegisterClass) else if (RC == Alpha::GPRCRegisterClass)
BuildMI(MBB, MI, DL, get(Alpha::STQ)) BuildMI(MBB, MI, DL, get(Alpha::STQ))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FrameIdx).addReg(Alpha::F31); .addFrameIndex(FrameIdx).addReg(Alpha::F31);
else else
abort(); abort();
@ -217,7 +217,7 @@ void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
abort(); abort();
DebugLoc DL = DebugLoc::getUnknownLoc(); DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = MachineInstrBuilder MIB =
BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
for (unsigned i = 0, e = Addr.size(); i != e; ++i) for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]); MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB); NewMIs.push_back(MIB);
@ -290,7 +290,7 @@ MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
Opc = (Opc == Alpha::BISr) ? Alpha::STQ : Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(InReg, false, false, isKill) .addReg(InReg, getKillRegState(isKill))
.addFrameIndex(FrameIndex) .addFrameIndex(FrameIndex)
.addReg(Alpha::F31); .addReg(Alpha::F31);
} else { // load -> move } else { // load -> move
@ -299,7 +299,7 @@ MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(OutReg, true, false, false, isDead) .addReg(OutReg, RegState::Define | getDeadRegState(isDead))
.addFrameIndex(FrameIndex) .addFrameIndex(FrameIndex)
.addReg(Alpha::F31); .addReg(Alpha::F31);
} }

8
lib/Target/CellSPU/SPUInstrInfo.cpp
View File

@ -320,7 +320,7 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
DebugLoc DL = DebugLoc::getUnknownLoc(); DebugLoc DL = DebugLoc::getUnknownLoc();
if (MI != MBB.end()) DL = MI->getDebugLoc(); if (MI != MBB.end()) DL = MI->getDebugLoc();
addFrameReference(BuildMI(MBB, MI, DL, get(opc)) addFrameReference(BuildMI(MBB, MI, DL, get(opc))
.addReg(SrcReg, false, false, isKill), FrameIdx); .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
} }
void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
@ -353,7 +353,7 @@ void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
} }
DebugLoc DL = DebugLoc::getUnknownLoc(); DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
.addReg(SrcReg, false, false, isKill); .addReg(SrcReg, getKillRegState(isKill));
for (unsigned i = 0, e = Addr.size(); i != e; ++i) for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]); MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB); NewMIs.push_back(MIB);
@ -495,7 +495,7 @@ SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(),
get(SPU::STQDr32)); get(SPU::STQDr32));
MIB.addReg(InReg, false, false, isKill); MIB.addReg(InReg, getKillRegState(isKill));
NewMI = addFrameReference(MIB, FrameIndex); NewMI = addFrameReference(MIB, FrameIndex);
} }
} else { // move -> load } else { // move -> load
@ -503,7 +503,7 @@ SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
bool isDead = MI->getOperand(0).isDead(); bool isDead = MI->getOperand(0).isDead();
MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)); MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc));
MIB.addReg(OutReg, true, false, false, isDead); MIB.addReg(OutReg, RegState::Define | getDeadRegState(isDead));
Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
? SPU::STQDr32 : SPU::STQXr32; ? SPU::STQDr32 : SPU::STQXr32;
NewMI = addFrameReference(MIB, FrameIndex); NewMI = addFrameReference(MIB, FrameIndex);

8
lib/Target/IA64/IA64InstrInfo.cpp
View File

@ -96,17 +96,17 @@ void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (RC == IA64::FPRegisterClass) { if (RC == IA64::FPRegisterClass) {
BuildMI(MBB, MI, DL, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx) BuildMI(MBB, MI, DL, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
.addReg(SrcReg, false, false, isKill); .addReg(SrcReg, getKillRegState(isKill));
} else if (RC == IA64::GRRegisterClass) { } else if (RC == IA64::GRRegisterClass) {
BuildMI(MBB, MI, DL, get(IA64::ST8)).addFrameIndex(FrameIdx) BuildMI(MBB, MI, DL, get(IA64::ST8)).addFrameIndex(FrameIdx)
.addReg(SrcReg, false, false, isKill); .addReg(SrcReg, getKillRegState(isKill));
} else if (RC == IA64::PRRegisterClass) { } else if (RC == IA64::PRRegisterClass) {
/* we use IA64::r2 as a temporary register for doing this hackery. */ /* we use IA64::r2 as a temporary register for doing this hackery. */
// first we load 0: // first we load 0:
BuildMI(MBB, MI, DL, get(IA64::MOV), IA64::r2).addReg(IA64::r0); BuildMI(MBB, MI, DL, get(IA64::MOV), IA64::r2).addReg(IA64::r0);
// then conditionally add 1: // then conditionally add 1:
BuildMI(MBB, MI, DL, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2) BuildMI(MBB, MI, DL, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
.addImm(1).addReg(SrcReg, false, false, isKill); .addImm(1).addReg(SrcReg, getKillRegState(isKill));
// and then store it to the stack // and then store it to the stack
BuildMI(MBB, MI, DL, get(IA64::ST8)) BuildMI(MBB, MI, DL, get(IA64::ST8))
.addFrameIndex(FrameIdx) .addFrameIndex(FrameIdx)
@ -136,7 +136,7 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
for (unsigned i = 0, e = Addr.size(); i != e; ++i) for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]); MIB.addOperand(Addr[i]);
MIB.addReg(SrcReg, false, false, isKill); MIB.addReg(SrcReg, getKillRegState(isKill));
NewMIs.push_back(MIB); NewMIs.push_back(MIB);
return; return;

6
lib/Target/MSP430/MSP430InstrInfo.cpp
View File

@ -38,11 +38,11 @@ void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (RC == &MSP430::GR16RegClass) if (RC == &MSP430::GR16RegClass)
BuildMI(MBB, MI, DL, get(MSP430::MOV16mr)) BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
.addFrameIndex(FrameIdx).addImm(0) .addFrameIndex(FrameIdx).addImm(0)
.addReg(SrcReg, false, false, isKill); .addReg(SrcReg, getKillRegState(isKill));
else if (RC == &MSP430::GR8RegClass) else if (RC == &MSP430::GR8RegClass)
BuildMI(MBB, MI, DL, get(MSP430::MOV8mr)) BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
.addFrameIndex(FrameIdx).addImm(0) .addFrameIndex(FrameIdx).addImm(0)
.addReg(SrcReg, false, false, isKill); .addReg(SrcReg, getKillRegState(isKill));
else else
assert(0 && "Cannot store this register to stack slot!"); assert(0 && "Cannot store this register to stack slot!");
} }
@ -129,7 +129,7 @@ MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
// Add the callee-saved register as live-in. It's killed at the spill. // Add the callee-saved register as live-in. It's killed at the spill.
MBB.addLiveIn(Reg); MBB.addLiveIn(Reg);
BuildMI(MBB, MI, DL, get(MSP430::PUSH16r)) BuildMI(MBB, MI, DL, get(MSP430::PUSH16r))
.addReg(Reg, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); .addReg(Reg, RegState::Kill);
} }
return true; return true;
} }

2
lib/Target/MSP430/MSP430RegisterInfo.cpp
View File

@ -241,7 +241,7 @@ void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const {
// Save FPW into the appropriate stack slot... // Save FPW into the appropriate stack slot...
BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
.addReg(MSP430::FPW, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); .addReg(MSP430::FPW, RegState::Kill);
// Update FPW with the new base value... // Update FPW with the new base value...
BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW) BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)

12
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -197,7 +197,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
Opc = Mips::SDC1; Opc = Mips::SDC1;
} }
BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, false, false, isKill) BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI); .addImm(0).addFrameIndex(FI);
} }
@ -217,7 +217,7 @@ void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
DebugLoc DL = DebugLoc::getUnknownLoc(); DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
.addReg(SrcReg, false, false, isKill); .addReg(SrcReg, getKillRegState(isKill));
for (unsigned i = 0, e = Addr.size(); i != e; ++i) for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]); MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB); NewMIs.push_back(MIB);
@ -285,13 +285,13 @@ foldMemoryOperandImpl(MachineFunction &MF,
unsigned SrcReg = MI->getOperand(2).getReg(); unsigned SrcReg = MI->getOperand(2).getReg();
bool isKill = MI->getOperand(2).isKill(); bool isKill = MI->getOperand(2).isKill();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI); .addImm(0).addFrameIndex(FI);
} else { // COPY -> LOAD } else { // COPY -> LOAD
unsigned DstReg = MI->getOperand(0).getReg(); unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead(); bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
.addReg(DstReg, true, false, false, isDead) .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addImm(0).addFrameIndex(FI); .addImm(0).addFrameIndex(FI);
} }
} }
@ -315,13 +315,13 @@ foldMemoryOperandImpl(MachineFunction &MF,
unsigned SrcReg = MI->getOperand(1).getReg(); unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill(); bool isKill = MI->getOperand(1).isKill();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI) ; .addImm(0).addFrameIndex(FI) ;
} else { // COPY -> LOAD } else { // COPY -> LOAD
unsigned DstReg = MI->getOperand(0).getReg(); unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead(); bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
.addReg(DstReg, true, false, false, isDead) .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addImm(0).addFrameIndex(FI); .addImm(0).addFrameIndex(FI);
} }
} }

4
lib/Target/PIC16/PIC16InstrInfo.cpp
View File

@ -83,7 +83,7 @@ void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
//MachineFunction &MF = *MBB.getParent(); //MachineFunction &MF = *MBB.getParent();
//MachineRegisterInfo &RI = MF.getRegInfo(); //MachineRegisterInfo &RI = MF.getRegInfo();
BuildMI(MBB, I, DL, get(PIC16::movwf)) BuildMI(MBB, I, DL, get(PIC16::movwf))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addImm(PTLI->GetTmpOffsetForFI(FI, 1)) .addImm(PTLI->GetTmpOffsetForFI(FI, 1))
.addExternalSymbol(tmpName) .addExternalSymbol(tmpName)
.addImm(1); // Emit banksel for it. .addImm(1); // Emit banksel for it.
@ -98,7 +98,7 @@ void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
unsigned opcode = (SrcReg == PIC16::FSR0) ? PIC16::save_fsr0 unsigned opcode = (SrcReg == PIC16::FSR0) ? PIC16::save_fsr0
: PIC16::save_fsr1; : PIC16::save_fsr1;
BuildMI(MBB, I, DL, get(opcode)) BuildMI(MBB, I, DL, get(opcode))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addImm(PTLI->GetTmpOffsetForFI(FI, 3)) .addImm(PTLI->GetTmpOffsetForFI(FI, 3))
.addExternalSymbol(tmpName) .addExternalSymbol(tmpName)
.addImm(1); // Emit banksel for it. .addImm(1); // Emit banksel for it.

64
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -175,9 +175,9 @@ PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
bool Reg0IsDead = MI->getOperand(0).isDead(); bool Reg0IsDead = MI->getOperand(0).isDead();
return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
.addReg(Reg0, true, false, false, Reg0IsDead) .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
.addReg(Reg2, false, false, Reg2IsKill) .addReg(Reg2, getKillRegState(Reg2IsKill))
.addReg(Reg1, false, false, Reg1IsKill) .addReg(Reg1, getKillRegState(Reg1IsKill))
.addImm((ME+1) & 31) .addImm((ME+1) & 31)
.addImm((MB-1) & 31); .addImm((MB-1) & 31);
} }
@ -370,7 +370,8 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
if (RC == PPC::GPRCRegisterClass) { if (RC == PPC::GPRCRegisterClass) {
if (SrcReg != PPC::LR) { if (SrcReg != PPC::LR) {
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
.addReg(SrcReg, false, false, isKill), .addReg(SrcReg,
getKillRegState(isKill)),
FrameIdx)); FrameIdx));
} else { } else {
// FIXME: this spills LR immediately to memory in one step. To do this, // FIXME: this spills LR immediately to memory in one step. To do this,
@ -378,33 +379,43 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
// a hack. // a hack.
NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
.addReg(PPC::R11, false, false, isKill), .addReg(PPC::R11,
getKillRegState(isKill)),
FrameIdx)); FrameIdx));
} }
} else if (RC == PPC::G8RCRegisterClass) { } else if (RC == PPC::G8RCRegisterClass) {
if (SrcReg != PPC::LR8) { if (SrcReg != PPC::LR8) {
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
.addReg(SrcReg, false, false, isKill), FrameIdx)); .addReg(SrcReg,
getKillRegState(isKill)),
FrameIdx));
} else { } else {
// FIXME: this spills LR immediately to memory in one step. To do this, // FIXME: this spills LR immediately to memory in one step. To do this,
// we use R11, which we know cannot be used in the prolog/epilog. This is // we use R11, which we know cannot be used in the prolog/epilog. This is
// a hack. // a hack.
NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
.addReg(PPC::X11, false, false, isKill), FrameIdx)); .addReg(PPC::X11,
getKillRegState(isKill)),
FrameIdx));
} }
} else if (RC == PPC::F8RCRegisterClass) { } else if (RC == PPC::F8RCRegisterClass) {
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
.addReg(SrcReg, false, false, isKill), FrameIdx)); .addReg(SrcReg,
getKillRegState(isKill)),
FrameIdx));
} else if (RC == PPC::F4RCRegisterClass) { } else if (RC == PPC::F4RCRegisterClass) {
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
.addReg(SrcReg, false, false, isKill), FrameIdx)); .addReg(SrcReg,
getKillRegState(isKill)),
FrameIdx));
} else if (RC == PPC::CRRCRegisterClass) { } else if (RC == PPC::CRRCRegisterClass) {
if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
(EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
// FIXME (64-bit): Enable // FIXME (64-bit): Enable
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
.addReg(SrcReg, false, false, isKill), .addReg(SrcReg,
getKillRegState(isKill)),
FrameIdx)); FrameIdx));
return true; return true;
} else { } else {
@ -423,7 +434,8 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
} }
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
.addReg(PPC::R0, false, false, isKill), .addReg(PPC::R0,
getKillRegState(isKill)),
FrameIdx)); FrameIdx));
} }
} else if (RC == PPC::CRBITRCRegisterClass) { } else if (RC == PPC::CRBITRCRegisterClass) {
@ -461,7 +473,9 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
FrameIdx, 0, 0)); FrameIdx, 0, 0));
NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
.addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0)); .addReg(SrcReg, getKillRegState(isKill))
.addReg(PPC::R0)
.addReg(PPC::R0));
} else { } else {
assert(0 && "Unknown regclass!"); assert(0 && "Unknown regclass!");
abort(); abort();
@ -519,7 +533,7 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
abort(); abort();
} }
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
.addReg(SrcReg, false, false, isKill); .addReg(SrcReg, getKillRegState(isKill));
for (unsigned i = 0, e = Addr.size(); i != e; ++i) for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]); MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB); NewMIs.push_back(MIB);
@ -678,13 +692,15 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
unsigned InReg = MI->getOperand(1).getReg(); unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill(); bool isKill = MI->getOperand(1).isKill();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW)) NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
.addReg(InReg, false, false, isKill), .addReg(InReg, getKillRegState(isKill)),
FrameIndex); FrameIndex);
} else { // move -> load } else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg(); unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead(); bool isDead = MI->getOperand(0).isDead();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ)) NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
.addReg(OutReg, true, false, false, isDead), .addReg(OutReg,
RegState::Define |
getDeadRegState(isDead)),
FrameIndex); FrameIndex);
} }
} else if ((Opc == PPC::OR8 && } else if ((Opc == PPC::OR8 &&
@ -693,13 +709,15 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
unsigned InReg = MI->getOperand(1).getReg(); unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill(); bool isKill = MI->getOperand(1).isKill();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD)) NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
.addReg(InReg, false, false, isKill), .addReg(InReg, getKillRegState(isKill)),
FrameIndex); FrameIndex);
} else { // move -> load } else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg(); unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead(); bool isDead = MI->getOperand(0).isDead();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD)) NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
.addReg(OutReg, true, false, false, isDead), .addReg(OutReg,
RegState::Define |
getDeadRegState(isDead)),
FrameIndex); FrameIndex);
} }
} else if (Opc == PPC::FMRD) { } else if (Opc == PPC::FMRD) {
@ -707,13 +725,15 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
unsigned InReg = MI->getOperand(1).getReg(); unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill(); bool isKill = MI->getOperand(1).isKill();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD)) NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD))
.addReg(InReg, false, false, isKill), .addReg(InReg, getKillRegState(isKill)),
FrameIndex); FrameIndex);
} else { // move -> load } else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg(); unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead(); bool isDead = MI->getOperand(0).isDead();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD)) NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD))
.addReg(OutReg, true, false, false, isDead), .addReg(OutReg,
RegState::Define |
getDeadRegState(isDead)),
FrameIndex); FrameIndex);
} }
} else if (Opc == PPC::FMRS) { } else if (Opc == PPC::FMRS) {
@ -721,13 +741,15 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
unsigned InReg = MI->getOperand(1).getReg(); unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill(); bool isKill = MI->getOperand(1).isKill();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS)) NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS))
.addReg(InReg, false, false, isKill), .addReg(InReg, getKillRegState(isKill)),
FrameIndex); FrameIndex);
} else { // move -> load } else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg(); unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead(); bool isDead = MI->getOperand(0).isDead();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS)) NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS))
.addReg(OutReg, true, false, false, isDead), .addReg(OutReg,
RegState::Define |
getDeadRegState(isDead)),
FrameIndex); FrameIndex);
} }
} }

40
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -437,7 +437,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
.addImm(CalleeAmt >> 16); .addImm(CalleeAmt >> 16);
BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
.addReg(TmpReg, false, false, true) .addReg(TmpReg, RegState::Kill)
.addImm(CalleeAmt & 0xFFFF); .addImm(CalleeAmt & 0xFFFF);
BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
.addReg(StackReg) .addReg(StackReg)
@ -537,12 +537,12 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
if (LP64) { if (LP64) {
if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
.addReg(Reg, false, false, true) .addReg(Reg, RegState::Kill)
.addReg(PPC::X1) .addReg(PPC::X1)
.addReg(MI.getOperand(1).getReg()); .addReg(MI.getOperand(1).getReg());
else else
BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
.addReg(PPC::X0, false, false, true) .addReg(PPC::X0, RegState::Kill)
.addReg(PPC::X1) .addReg(PPC::X1)
.addReg(MI.getOperand(1).getReg()); .addReg(MI.getOperand(1).getReg());
@ -555,10 +555,10 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
.addReg(PPC::X1) .addReg(PPC::X1)
.addImm(maxCallFrameSize) .addImm(maxCallFrameSize)
.addReg(MI.getOperand(1).getReg(), false, true, true); .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
} else { } else {
BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
.addReg(Reg, false, false, true) .addReg(Reg, RegState::Kill)
.addReg(PPC::R1) .addReg(PPC::R1)
.addReg(MI.getOperand(1).getReg()); .addReg(MI.getOperand(1).getReg());
@ -571,7 +571,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
.addReg(PPC::R1) .addReg(PPC::R1)
.addImm(maxCallFrameSize) .addImm(maxCallFrameSize)
.addReg(MI.getOperand(1).getReg(), false, true, true); .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
} }
// Discard the DYNALLOC instruction. // Discard the DYNALLOC instruction.
@ -607,7 +607,7 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
else else
// Implicitly kill the CR register. // Implicitly kill the CR register.
BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg) BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg)
.addReg(MI.getOperand(0).getReg(), false, true, true); .addReg(MI.getOperand(0).getReg(), RegState::ImplicitKill);
// If the saved register wasn't CR0, shift the bits left so that they are in // If the saved register wasn't CR0, shift the bits left so that they are in
// CR0's slot. // CR0's slot.
@ -615,13 +615,13 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
if (SrcReg != PPC::CR0) if (SrcReg != PPC::CR0)
// rlwinm rA, rA, ShiftBits, 0, 31. // rlwinm rA, rA, ShiftBits, 0, 31.
BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
.addReg(Reg, false, false, true) .addReg(Reg, RegState::Kill)
.addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
.addImm(0) .addImm(0)
.addImm(31); .addImm(31);
addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
.addReg(Reg, false, false, MI.getOperand(1).getImm()), .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
FrameIndex); FrameIndex);
// Discard the pseudo instruction. // Discard the pseudo instruction.
@ -735,7 +735,7 @@ void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
.addImm(Offset >> 16); .addImm(Offset >> 16);
BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
.addReg(SReg, false, false, true) .addReg(SReg, RegState::Kill)
.addImm(Offset); .addImm(Offset);
// Convert into indexed form of the instruction: // Convert into indexed form of the instruction:
@ -861,7 +861,7 @@ static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
.addImm(UsedRegMask); .addImm(UsedRegMask);
else else
BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
.addReg(SrcReg, false, false, true) .addReg(SrcReg, RegState::Kill)
.addImm(UsedRegMask); .addImm(UsedRegMask);
} else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
if (DstReg != SrcReg) if (DstReg != SrcReg)
@ -870,7 +870,7 @@ static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
.addImm(UsedRegMask >> 16); .addImm(UsedRegMask >> 16);
else else
BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
.addReg(SrcReg, false, false, true) .addReg(SrcReg, RegState::Kill)
.addImm(UsedRegMask >> 16); .addImm(UsedRegMask >> 16);
} else { } else {
if (DstReg != SrcReg) if (DstReg != SrcReg)
@ -879,11 +879,11 @@ static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
.addImm(UsedRegMask >> 16); .addImm(UsedRegMask >> 16);
else else
BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
.addReg(SrcReg, false, false, true) .addReg(SrcReg, RegState::Kill)
.addImm(UsedRegMask >> 16); .addImm(UsedRegMask >> 16);
BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
.addReg(DstReg, false, false, true) .addReg(DstReg, RegState::Kill)
.addImm(UsedRegMask & 0xFFFF); .addImm(UsedRegMask & 0xFFFF);
} }
@ -1101,7 +1101,7 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
.addImm(32 - Log2_32(MaxAlign)) .addImm(32 - Log2_32(MaxAlign))
.addImm(31); .addImm(31);
BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
.addReg(PPC::R0, false, false, true) .addReg(PPC::R0, RegState::Kill)
.addImm(NegFrameSize); .addImm(NegFrameSize);
BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
.addReg(PPC::R1) .addReg(PPC::R1)
@ -1116,7 +1116,7 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
.addImm(NegFrameSize >> 16); .addImm(NegFrameSize >> 16);
BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
.addReg(PPC::R0, false, false, true) .addReg(PPC::R0, RegState::Kill)
.addImm(NegFrameSize & 0xFFFF); .addImm(NegFrameSize & 0xFFFF);
BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
.addReg(PPC::R1) .addReg(PPC::R1)
@ -1148,7 +1148,7 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
.addImm(NegFrameSize >> 16); .addImm(NegFrameSize >> 16);
BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
.addReg(PPC::X0, false, false, true) .addReg(PPC::X0, RegState::Kill)
.addImm(NegFrameSize & 0xFFFF); .addImm(NegFrameSize & 0xFFFF);
BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
.addReg(PPC::X1) .addReg(PPC::X1)
@ -1288,7 +1288,7 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
.addImm(FrameSize >> 16); .addImm(FrameSize >> 16);
BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
.addReg(PPC::R0, false, false, true) .addReg(PPC::R0, RegState::Kill)
.addImm(FrameSize & 0xFFFF); .addImm(FrameSize & 0xFFFF);
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
.addReg(PPC::R1) .addReg(PPC::R1)
@ -1312,7 +1312,7 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
.addImm(FrameSize >> 16); .addImm(FrameSize >> 16);
BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
.addReg(PPC::X0, false, false, true) .addReg(PPC::X0, RegState::Kill)
.addImm(FrameSize & 0xFFFF); .addImm(FrameSize & 0xFFFF);
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
.addReg(PPC::X1) .addReg(PPC::X1)
@ -1374,7 +1374,7 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
.addImm(CallerAllocatedAmt >> 16); .addImm(CallerAllocatedAmt >> 16);
BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
.addReg(TmpReg, false, false, true) .addReg(TmpReg, RegState::Kill)
.addImm(CallerAllocatedAmt & 0xFFFF); .addImm(CallerAllocatedAmt & 0xFFFF);
BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
.addReg(StackReg) .addReg(StackReg)

12
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -152,13 +152,13 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
// On the order of operands here: think "[FrameIdx + 0] = SrcReg". // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
if (RC == SP::IntRegsRegisterClass) if (RC == SP::IntRegsRegisterClass)
BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg, false, false, isKill); .addReg(SrcReg, getKillRegState(isKill));
else if (RC == SP::FPRegsRegisterClass) else if (RC == SP::FPRegsRegisterClass)
BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg, false, false, isKill); .addReg(SrcReg, getKillRegState(isKill));
else if (RC == SP::DFPRegsRegisterClass) else if (RC == SP::DFPRegsRegisterClass)
BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg, false, false, isKill); .addReg(SrcReg, getKillRegState(isKill));
else else
assert(0 && "Can't store this register to stack slot"); assert(0 && "Can't store this register to stack slot");
} }
@ -181,7 +181,7 @@ void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
for (unsigned i = 0, e = Addr.size(); i != e; ++i) for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]); MIB.addOperand(Addr[i]);
MIB.addReg(SrcReg, false, false, isKill); MIB.addReg(SrcReg, getKillRegState(isKill));
NewMIs.push_back(MIB); NewMIs.push_back(MIB);
return; return;
} }
@ -260,13 +260,13 @@ MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
get(isFloat ? SP::STFri : SP::STDFri)) get(isFloat ? SP::STFri : SP::STDFri))
.addFrameIndex(FI) .addFrameIndex(FI)
.addImm(0) .addImm(0)
.addReg(SrcReg, false, false, isKill); .addReg(SrcReg, getKillRegState(isKill));
} else { // COPY -> LOAD } else { // COPY -> LOAD
unsigned DstReg = MI->getOperand(0).getReg(); unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead(); bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), NewMI = BuildMI(MF, MI->getDebugLoc(),
get(isFloat ? SP::LDFri : SP::LDDFri)) get(isFloat ? SP::LDFri : SP::LDDFri))
.addReg(DstReg, true, false, false, isDead) .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addFrameIndex(FI) .addFrameIndex(FI)
.addImm(0); .addImm(0);
} }

8
lib/Target/X86/X86InstrBuilder.h
View File

@ -83,13 +83,13 @@ inline const MachineInstrBuilder &addOffset(const MachineInstrBuilder &MIB,
inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB, inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
unsigned Reg, bool isKill, unsigned Reg, bool isKill,
int Offset) { int Offset) {
return addOffset(MIB.addReg(Reg, false, false, isKill), Offset); return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
} }
inline const MachineInstrBuilder &addLeaRegOffset(const MachineInstrBuilder &MIB, inline const MachineInstrBuilder &addLeaRegOffset(const MachineInstrBuilder &MIB,
unsigned Reg, bool isKill, unsigned Reg, bool isKill,
int Offset) { int Offset) {
return addLeaOffset(MIB.addReg(Reg, false, false, isKill), Offset); return addLeaOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
} }
/// addRegReg - This function is used to add a memory reference of the form: /// addRegReg - This function is used to add a memory reference of the form:
@ -97,8 +97,8 @@ inline const MachineInstrBuilder &addLeaRegOffset(const MachineInstrBuilder &MIB
inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
unsigned Reg1, bool isKill1, unsigned Reg1, bool isKill1,
unsigned Reg2, bool isKill2) { unsigned Reg2, bool isKill2) {
return MIB.addReg(Reg1, false, false, isKill1).addImm(1) return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
.addReg(Reg2, false, false, isKill2).addImm(0); .addReg(Reg2, getKillRegState(isKill2)).addImm(0);
} }
inline const MachineInstrBuilder &addLeaAddress(const MachineInstrBuilder &MIB, inline const MachineInstrBuilder &addLeaAddress(const MachineInstrBuilder &MIB,

74
lib/Target/X86/X86InstrInfo.cpp
View File

@ -1032,8 +1032,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned A = MI->getOperand(0).getReg(); unsigned A = MI->getOperand(0).getReg();
unsigned M = MI->getOperand(3).getImm(); unsigned M = MI->getOperand(3).getImm();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
.addReg(A, true, false, false, isDead) .addReg(A, RegState::Define | getDeadRegState(isDead))
.addReg(B, false, false, isKill).addImm(M); .addReg(B, getKillRegState(isKill)).addImm(M);
break; break;
} }
case X86::SHL64ri: { case X86::SHL64ri: {
@ -1044,8 +1044,10 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
if (ShAmt == 0 || ShAmt >= 4) return 0; if (ShAmt == 0 || ShAmt >= 4) return 0;
NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
.addReg(Dest, true, false, false, isDead) .addReg(Dest, RegState::Define | getDeadRegState(isDead))
.addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0); .addReg(0).addImm(1 << ShAmt)
.addReg(Src, getKillRegState(isKill))
.addImm(0);
break; break;
} }
case X86::SHL32ri: { case X86::SHL32ri: {
@ -1058,9 +1060,9 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ? unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
X86::LEA64_32r : X86::LEA32r; X86::LEA64_32r : X86::LEA32r;
NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead) .addReg(Dest, RegState::Define | getDeadRegState(isDead))
.addReg(0).addImm(1 << ShAmt) .addReg(0).addImm(1 << ShAmt)
.addReg(Src, false, false, isKill).addImm(0); .addReg(Src, getKillRegState(isKill)).addImm(0);
break; break;
} }
case X86::SHL16ri: { case X86::SHL16ri: {
@ -1083,17 +1085,20 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
MachineInstr *InsMI = MachineInstr *InsMI =
BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg) BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
.addReg(leaInReg).addReg(Src, false, false, isKill) .addReg(leaInReg)
.addReg(Src, getKillRegState(isKill))
.addImm(X86::SUBREG_16BIT); .addImm(X86::SUBREG_16BIT);
NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg) NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
.addReg(0).addImm(1 << ShAmt) .addReg(0).addImm(1 << ShAmt)
.addReg(leaInReg, false, false, true).addImm(0); .addReg(leaInReg, RegState::Kill)
.addImm(0);
MachineInstr *ExtMI = MachineInstr *ExtMI =
BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG)) BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
.addReg(Dest, true, false, false, isDead) .addReg(Dest, RegState::Define | getDeadRegState(isDead))
.addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT); .addReg(leaOutReg, RegState::Kill)
.addImm(X86::SUBREG_16BIT);
if (LV) { if (LV) {
// Update live variables // Update live variables
@ -1107,9 +1112,10 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
return ExtMI; return ExtMI;
} else { } else {
NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead) .addReg(Dest, RegState::Define | getDeadRegState(isDead))
.addReg(0).addImm(1 << ShAmt) .addReg(0).addImm(1 << ShAmt)
.addReg(Src, false, false, isKill).addImm(0); .addReg(Src, getKillRegState(isKill))
.addImm(0);
} }
break; break;
} }
@ -1130,7 +1136,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
: (is64Bit ? X86::LEA64_32r : X86::LEA32r); : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead), .addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Src, isKill, 1); Src, isKill, 1);
break; break;
} }
@ -1139,7 +1146,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
if (DisableLEA16) return 0; if (DisableLEA16) return 0;
assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead), .addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Src, isKill, 1); Src, isKill, 1);
break; break;
case X86::DEC64r: case X86::DEC64r:
@ -1149,7 +1157,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
: (is64Bit ? X86::LEA64_32r : X86::LEA32r); : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead), .addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Src, isKill, -1); Src, isKill, -1);
break; break;
} }
@ -1158,7 +1167,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
if (DisableLEA16) return 0; if (DisableLEA16) return 0;
assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead), .addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Src, isKill, -1); Src, isKill, -1);
break; break;
case X86::ADD64rr: case X86::ADD64rr:
@ -1169,7 +1179,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned Src2 = MI->getOperand(2).getReg(); unsigned Src2 = MI->getOperand(2).getReg();
bool isKill2 = MI->getOperand(2).isKill(); bool isKill2 = MI->getOperand(2).isKill();
NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead), .addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Src, isKill, Src2, isKill2); Src, isKill, Src2, isKill2);
if (LV && isKill2) if (LV && isKill2)
LV->replaceKillInstruction(Src2, MI, NewMI); LV->replaceKillInstruction(Src2, MI, NewMI);
@ -1181,7 +1192,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned Src2 = MI->getOperand(2).getReg(); unsigned Src2 = MI->getOperand(2).getReg();
bool isKill2 = MI->getOperand(2).isKill(); bool isKill2 = MI->getOperand(2).isKill();
NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead), .addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Src, isKill, Src2, isKill2); Src, isKill, Src2, isKill2);
if (LV && isKill2) if (LV && isKill2)
LV->replaceKillInstruction(Src2, MI, NewMI); LV->replaceKillInstruction(Src2, MI, NewMI);
@ -1192,7 +1204,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImm()) if (MI->getOperand(2).isImm())
NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
.addReg(Dest, true, false, false, isDead), .addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Src, isKill, MI->getOperand(2).getImm()); Src, isKill, MI->getOperand(2).getImm());
break; break;
case X86::ADD32ri: case X86::ADD32ri:
@ -1201,7 +1214,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
if (MI->getOperand(2).isImm()) { if (MI->getOperand(2).isImm()) {
unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead), .addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Src, isKill, MI->getOperand(2).getImm()); Src, isKill, MI->getOperand(2).getImm());
} }
break; break;
@ -1211,7 +1225,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImm()) if (MI->getOperand(2).isImm())
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead), .addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Src, isKill, MI->getOperand(2).getImm()); Src, isKill, MI->getOperand(2).getImm());
break; break;
case X86::SHL16ri: case X86::SHL16ri:
@ -1229,7 +1244,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
: (MIOpc == X86::SHL32ri : (MIOpc == X86::SHL32ri
? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r); ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc)) NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead), AM); .addReg(Dest, RegState::Define |
getDeadRegState(isDead)), AM);
if (isKill) if (isKill)
NewMI->getOperand(3).setIsKill(true); NewMI->getOperand(3).setIsKill(true);
} }
@ -1870,7 +1886,7 @@ void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
DebugLoc DL = DebugLoc::getUnknownLoc(); DebugLoc DL = DebugLoc::getUnknownLoc();
if (MI != MBB.end()) DL = MI->getDebugLoc(); if (MI != MBB.end()) DL = MI->getDebugLoc();
addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
.addReg(SrcReg, false, false, isKill); .addReg(SrcReg, getKillRegState(isKill));
} }
void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
@ -1885,7 +1901,7 @@ void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
for (unsigned i = 0, e = Addr.size(); i != e; ++i) for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]); MIB.addOperand(Addr[i]);
MIB.addReg(SrcReg, false, false, isKill); MIB.addReg(SrcReg, getKillRegState(isKill));
NewMIs.push_back(MIB); NewMIs.push_back(MIB);
} }
@ -2001,7 +2017,7 @@ bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
// Add the callee-saved register as live-in. It's killed at the spill. // Add the callee-saved register as live-in. It's killed at the spill.
MBB.addLiveIn(Reg); MBB.addLiveIn(Reg);
BuildMI(MBB, MI, DL, get(Opc)) BuildMI(MBB, MI, DL, get(Opc))
.addReg(Reg, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); .addReg(Reg, RegState::Kill);
} }
return true; return true;
} }
@ -2396,7 +2412,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
MachineInstrBuilder MIB(DataMI); MachineInstrBuilder MIB(DataMI);
if (FoldedStore) if (FoldedStore)
MIB.addReg(Reg, true); MIB.addReg(Reg, RegState::Define);
for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
MIB.addOperand(BeforeOps[i]); MIB.addOperand(BeforeOps[i]);
if (FoldedLoad) if (FoldedLoad)
@ -2405,7 +2421,11 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
MIB.addOperand(AfterOps[i]); MIB.addOperand(AfterOps[i]);
for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
MachineOperand &MO = ImpOps[i]; MachineOperand &MO = ImpOps[i];
MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead()); MIB.addReg(MO.getReg(),
getDefRegState(MO.isDef()) |
RegState::Implicit |
getKillRegState(MO.isKill()) |
getDeadRegState(MO.isDead()));
} }
// Change CMP32ri r, 0 back to TEST32rr r, r, etc. // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
unsigned NewOpc = 0; unsigned NewOpc = 0;

4
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -789,7 +789,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
// Save EBP into the appropriate stack slot... // Save EBP into the appropriate stack slot...
BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
.addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); .addReg(FramePtr, RegState::Kill);
if (needsFrameMoves) { if (needsFrameMoves) {
// Mark effective beginning of when frame pointer becomes valid. // Mark effective beginning of when frame pointer becomes valid.
@ -860,7 +860,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
} else { } else {
// Save EAX // Save EAX
BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r)) BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
.addReg(X86::EAX, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); .addReg(X86::EAX, RegState::Kill);
// Allocate NumBytes-4 bytes on stack. We'll also use 4 already // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
// allocated bytes for EAX. // allocated bytes for EAX.
BuildMI(MBB, MBBI, DL, BuildMI(MBB, MBBI, DL,

2
lib/Target/XCore/XCoreInstrInfo.cpp
View File

@ -397,7 +397,7 @@ void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
DebugLoc DL = DebugLoc::getUnknownLoc(); DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc(); if (I != MBB.end()) DL = I->getDebugLoc();
BuildMI(MBB, I, DL, get(XCore::STWFI)) BuildMI(MBB, I, DL, get(XCore::STWFI))
.addReg(SrcReg, false, false, isKill) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FrameIndex) .addFrameIndex(FrameIndex)
.addImm(0); .addImm(0);
} }

12
lib/Target/XCore/XCoreRegisterInfo.cpp
View File

@ -237,18 +237,18 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
case XCore::LDWFI: case XCore::LDWFI:
New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
.addReg(FramePtr) .addReg(FramePtr)
.addReg(ScratchReg, false, false, true); .addReg(ScratchReg, RegState::Kill);
break; break;
case XCore::STWFI: case XCore::STWFI:
New = BuildMI(MBB, II, dl, TII.get(XCore::STW_3r)) New = BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
.addReg(Reg, false, false, isKill) .addReg(Reg, getKillRegState(isKill))
.addReg(FramePtr) .addReg(FramePtr)
.addReg(ScratchReg, false, false, true); .addReg(ScratchReg, RegState::Kill);
break; break;
case XCore::LDAWFI: case XCore::LDAWFI:
New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
.addReg(FramePtr) .addReg(FramePtr)
.addReg(ScratchReg, false, false, true); .addReg(ScratchReg, RegState::Kill);
break; break;
default: default:
assert(0 && "Unexpected Opcode\n"); assert(0 && "Unexpected Opcode\n");
@ -262,7 +262,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
break; break;
case XCore::STWFI: case XCore::STWFI:
New = BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) New = BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
.addReg(Reg, false, false, isKill) .addReg(Reg, getKillRegState(isKill))
.addReg(FramePtr) .addReg(FramePtr)
.addImm(Offset); .addImm(Offset);
break; break;
@ -293,7 +293,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
case XCore::STWFI: case XCore::STWFI:
NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
BuildMI(MBB, II, dl, TII.get(NewOpcode)) BuildMI(MBB, II, dl, TII.get(NewOpcode))
.addReg(Reg, false, false, isKill) .addReg(Reg, getKillRegState(isKill))
.addImm(Offset); .addImm(Offset);
break; break;
case XCore::LDAWFI: case XCore::LDAWFI: