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Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127459 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -58,6 +58,10 @@ STATISTIC(NumMemoryInsts, "Number of memory instructions whose address "
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STATISTIC(NumExtsMoved, "Number of [s|z]ext instructions combined with loads");
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STATISTIC(NumExtUses, "Number of uses of [s|z]ext instructions optimized");
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static cl::opt<bool> DisableBranchOpts(
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"disable-cgp-branch-opts", cl::Hidden, cl::init(false),
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cl::desc("Disable branch optimizations in CodeGenPrepare"));
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namespace {
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class CodeGenPrepare : public FunctionPass {
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/// TLI - Keep a pointer of a TargetLowering to consult for determining
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@ -130,6 +134,16 @@ bool CodeGenPrepare::runOnFunction(Function &F) {
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SunkAddrs.clear();
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if (!DisableBranchOpts) {
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MadeChange = false;
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for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
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MadeChange |= ConstantFoldTerminator(BB);
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if (MadeChange && DT)
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DT->DT->recalculate(F);
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EverMadeChange |= MadeChange;
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}
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return EverMadeChange;
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}
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=arm | FileCheck %s
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; RUN: llc < %s -march=arm -disable-cgp-branch-opts | FileCheck %s
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define i32 @f1() {
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; CHECK: f1
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@ -1,4 +1,4 @@
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;RUN: llc --march=cellspu %s -o - | FileCheck %s
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;RUN: llc --march=cellspu -disable-cgp-branch-opts %s -o - | FileCheck %s
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; This is to check that emitting jumptables doesn't crash llc
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define i32 @test(i32 %param) {
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entry:
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
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; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts | FileCheck %s
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%struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
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%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
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@ -8,7 +8,7 @@ entry:
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; CHECK: sub sp, #8
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; CHECK: push
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; CHECK: add r7, sp, #4
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; CHECK: subs r4, r7, #4
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; CHECK: sub.w r4, r7, #4
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; CHECK: mov sp, r4
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; CHECK-NOT: mov sp, r7
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; CHECK: add sp, #8
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-cgp-branch-opts | FileCheck %s
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%struct.pix_pos = type { i32, i32, i32, i32, i32, i32 }
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@ -8,7 +8,7 @@ declare void @bar() nounwind optsize
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define void @foo() nounwind optsize {
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; CHECK: foo:
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; CHECK: push
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; CHECK: add r7, sp, #4
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; CHECK: mov r7, sp
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; CHECK: sub sp, #4
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entry:
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%m.i = alloca %struct.buf*, align 4
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@ -6,8 +6,6 @@ entry:
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br label %bb5
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bb5: ; preds = %bb5, %entry
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; CHECK: %bb5
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; CHECK: bne
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br i1 undef, label %bb5, label %bb.nph
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bb.nph: ; preds = %bb5
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=i386-apple-darwin | grep movw | not grep {, %e}
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; RUN: llc < %s -mtriple=i386-apple-darwin -disable-cgp-branch-opts | grep movw | not grep {, %e}
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%struct.DBC_t = type { i32, i8*, i16, %struct.DBC_t*, i8*, i8*, i8*, i8*, i8*, %struct.DBC_t*, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16, i32*, i8, i16, %struct.DRVOPT*, i16 }
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%struct.DRVOPT = type { i16, i32, i8, %struct.DRVOPT* }
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=x86_64-appel-darwin -stats |& grep {machine-sink}
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; RUN: llc < %s -mtriple=x86_64-appel-darwin -disable-cgp-branch-opts -stats |& grep {machine-sink}
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define fastcc void @t() nounwind ssp {
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entry:
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@ -1,5 +1,5 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s -check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -mtriple=i386-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X32
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; PR1632
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define void @_Z1fv() {
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=x86 | grep movzbl
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; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | grep movzbl
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; PR3366
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define void @_ada_c34002a() nounwind {
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=32
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; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=64
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; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | FileCheck %s -check-prefix=32
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; RUN: llc < %s -march=x86-64 -disable-cgp-branch-opts | FileCheck %s -check-prefix=64
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; rdar://7573216
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; PR6146
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@ -13,6 +13,7 @@ if.end: ; preds = %if.end.i
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; CHECK: %if.end
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; CHECK: movl (%{{.*}}), [[REG:%[a-z]+]]
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; CHECK-NOT: movl [[REG]], [[REG]]
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; CHECK-NEXT: testl [[REG]], [[REG]]
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; CHECK-NEXT: xorb
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%tmp138 = select i1 undef, i32 0, i32 %tmp7.i
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%tmp867 = zext i32 %tmp138 to i64
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@ -1,4 +1,4 @@
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;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding < %s | FileCheck %s
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;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding -disable-cgp-branch-opts < %s | FileCheck %s
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;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
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@ -14,13 +14,14 @@ entry:
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br i1 %1, label %T, label %trap
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; CHECK: entry:
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; HECK-NEXT: ret i32 4
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; CHECK-NEXT: br label %T
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trap: ; preds = %0, %entry
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tail call void @llvm.trap() noreturn nounwind
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unreachable
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T:
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; CHECK: ret i32 4
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ret i32 4
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}
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