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Group the scheduling functions together.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209339 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2014-05-21 23:40:18 +00:00
parent 8a0240ddf2
commit 595bdb7e8b
1 changed files with 5 additions and 4 deletions
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9
include/llvm/Target/TargetSubtargetInfo.h
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@ -76,6 +76,11 @@ public:
MachineInstr *end,
unsigned NumRegionInstrs) const {}
// \brief Perform target specific adjustments to the latency of a schedule
// dependency.
virtual void adjustSchedDependency(SUnit *def, SUnit *use,
SDep& dep) const { }
// enablePostRAScheduler - If the target can benefit from post-regalloc
// scheduling and the specified optimization level meets the requirement
// return true to enable post-register-allocation scheduling. In
@ -84,10 +89,6 @@ public:
virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const;
// adjustSchedDependency - Perform target specific adjustments to
// the latency of a schedule dependency.
virtual void adjustSchedDependency(SUnit *def, SUnit *use,
SDep& dep) const { }
/// \brief Enable use of alias analysis during code generation (during MI
/// scheduling, DAGCombine, etc.).