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Add support for the "Y" register, used by MUL & DIV.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12734 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2004-04-07 04:01:11 +00:00
parent e88c9dc860
commit 59e04e4889
2 changed files with 18 additions and 0 deletions
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9
lib/Target/Sparc/SparcRegisterInfo.td
View File

@ -24,6 +24,15 @@ class Rf<bits<5> num> : Register {
class Rd<bits<5> num> : Register {
field bits<5> Num = num;
}
// Rs - Special "ancillary state registers"
class Rs<bits<5> num> : Register {
field bits<5> Num = num;
}
// Special register used for multiplies and divides
let Namespace = "V8" in {
def Y : Rs<0>;
}
let Namespace = "V8" in {
def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>;

9
lib/Target/SparcV8/SparcV8RegisterInfo.td
View File

@ -24,6 +24,15 @@ class Rf<bits<5> num> : Register {
class Rd<bits<5> num> : Register {
field bits<5> Num = num;
}
// Rs - Special "ancillary state registers"
class Rs<bits<5> num> : Register {
field bits<5> Num = num;
}
// Special register used for multiplies and divides
let Namespace = "V8" in {
def Y : Rs<0>;
}
let Namespace = "V8" in {
def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>;