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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-14 17:34:41 +00:00
Fix fallout from 12-bit stuff landing: decide whether 20 bit displacements are needed during elimination of frame indexes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75989 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -323,3 +323,47 @@ SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
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return get(Opc);
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}
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const TargetInstrDesc&
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SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
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switch (Opc) {
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case SystemZ::MOV32mr:
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Opc = SystemZ::MOV32mry;
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break;
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case SystemZ::MOV32rm:
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Opc = SystemZ::MOV32rmy;
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break;
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case SystemZ::MOVSX32rm16:
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Opc = SystemZ::MOVSX32rm16y;
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break;
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case SystemZ::MOV32m8r:
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Opc = SystemZ::MOV32m8ry;
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break;
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case SystemZ::MOV32m16r:
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Opc = SystemZ::MOV32m16ry;
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break;
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case SystemZ::MOV64m8r:
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Opc = SystemZ::MOV64m8ry;
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break;
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case SystemZ::MOV64m16r:
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Opc = SystemZ::MOV64m16ry;
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break;
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case SystemZ::MOV64m32r:
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Opc = SystemZ::MOV64m32ry;
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break;
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case SystemZ::MUL32rm:
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Opc = SystemZ::MUL32rmy;
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break;
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case SystemZ::CMP32rm:
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Opc = SystemZ::CMP32rmy;
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break;
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case SystemZ::UCMP32rm:
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Opc = SystemZ::UCMP32rmy;
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break;
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default:
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break;
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}
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return get(Opc);
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}
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@ -67,6 +67,7 @@ public:
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const SmallVectorImpl<MachineOperand> &Cond) const;
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const TargetInstrDesc& getBrCond(SystemZCC::CondCodes CC) const;
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const TargetInstrDesc& getLongDispOpc(unsigned Opc) const;
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};
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}
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@ -12,6 +12,7 @@
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "SystemZInstrInfo.h"
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#include "SystemZMachineFunctionInfo.h"
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#include "SystemZRegisterInfo.h"
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#include "SystemZSubtarget.h"
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@ -27,7 +28,7 @@
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using namespace llvm;
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SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
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const TargetInstrInfo &tii)
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const SystemZInstrInfo &tii)
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: SystemZGenRegisterInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
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TM(tm), TII(tii) {
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}
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@ -124,9 +125,14 @@ void SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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// displacement field.
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MI.getOperand(i).ChangeToRegister(BasePtr, false);
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// Offset is a 20-bit integer.
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// Offset is a either 12-bit unsigned or 20-bit signed integer.
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// FIXME: handle "too long" displacements.
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int Offset = getFrameIndexOffset(MF, FrameIndex) + MI.getOperand(i+1).getImm();
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// Check whether displacement is too long to fit into 12 bit zext field.
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if (Offset < 0 || Offset >= 4096)
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MI.setDesc(TII.getLongDispOpc(MI.getOpcode()));
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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}
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@ -29,14 +29,14 @@ namespace SystemZ {
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}
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class SystemZSubtarget;
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class TargetInstrInfo;
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class SystemZInstrInfo;
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class Type;
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struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
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SystemZTargetMachine &TM;
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const TargetInstrInfo &TII;
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const SystemZInstrInfo &TII;
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SystemZRegisterInfo(SystemZTargetMachine &tm, const TargetInstrInfo &tii);
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SystemZRegisterInfo(SystemZTargetMachine &tm, const SystemZInstrInfo &tii);
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/// Code Generation virtual methods...
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const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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