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LSR: Fix the parameters used to compute the scaling factor cost.
Prior to this change, the considered addressing modes may be invalid since the maximum and minimum offsets were not taking into account. This was causing an assertion failure. The added test case exercices that behavior. <rdar://problem/14199725> Assertion failed: (CurScaleCost >= 0 && "Legal addressing mode has an illegal cost!") git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184341 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1417,11 +1417,19 @@ static unsigned getScalingFactorCost(const TargetTransformInfo &TTI,
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switch (LU.Kind) {
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case LSRUse::Address: {
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int CurScaleCost = TTI.getScalingFactorCost(LU.AccessTy, F.BaseGV,
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F.BaseOffset, F.HasBaseReg,
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F.Scale);
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assert(CurScaleCost >= 0 && "Legal addressing mode has an illegal cost!");
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return CurScaleCost;
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// Check the scaling factor cost with both the min and max offsets.
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int ScaleCostMinOffset =
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TTI.getScalingFactorCost(LU.AccessTy, F.BaseGV,
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F.BaseOffset + LU.MinOffset,
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F.HasBaseReg, F.Scale);
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int ScaleCostMaxOffset =
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TTI.getScalingFactorCost(LU.AccessTy, F.BaseGV,
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F.BaseOffset + LU.MaxOffset,
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F.HasBaseReg, F.Scale);
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assert(ScaleCostMinOffset >= 0 && ScaleCostMaxOffset >= 0 &&
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"Legal addressing mode has an illegal cost!");
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return std::max(ScaleCostMinOffset, ScaleCostMaxOffset);
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}
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case LSRUse::ICmpZero:
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// ICmpZero BaseReg + -1*ScaleReg => ICmp BaseReg, ScaleReg.
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@ -0,0 +1,68 @@
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; RUN: opt -loop-reduce %s -S -o - | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"
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target triple = "i686-pc-win32"
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; <rdar://problem/14199725> Assertion failed: (CurScaleCost >= 0 && "Legal addressing mode has an illegal cost!")
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; CHECK: @scalingFactorCrash
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define void @scalingFactorCrash() {
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br i1 undef, label %1, label %24
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; <label>:1 ; preds = %0
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br i1 undef, label %2, label %24
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; <label>:2 ; preds = %1
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br i1 undef, label %3, label %24
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; <label>:3 ; preds = %2
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br i1 undef, label %4, label %24
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; <label>:4 ; preds = %3
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br i1 undef, label %24, label %6
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; <label>:5 ; preds = %6
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br i1 undef, label %24, label %7
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; <label>:6 ; preds = %6, %4
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br i1 undef, label %6, label %5
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; <label>:7 ; preds = %9, %5
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br label %8
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; <label>:8 ; preds = %8, %7
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br i1 undef, label %9, label %8
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; <label>:9 ; preds = %8
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br i1 undef, label %7, label %10
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; <label>:10 ; preds = %9
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br i1 undef, label %24, label %11
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; <label>:11 ; preds = %10
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br i1 undef, label %15, label %13
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; <label>:12 ; preds = %14
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br label %15
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; <label>:13 ; preds = %11
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br label %14
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; <label>:14 ; preds = %14, %13
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br i1 undef, label %14, label %12
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; <label>:15 ; preds = %12, %11
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br i1 undef, label %16, label %24
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; <label>:16 ; preds = %16, %15
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%17 = phi i32 [ %21, %16 ], [ undef, %15 ]
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%18 = sub i32 %17, 1623127498
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%19 = getelementptr inbounds i32* undef, i32 %18
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store i32 undef, i32* %19, align 4
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%20 = add i32 %17, 1623127499
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%21 = add i32 %20, -1623127498
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%22 = add i32 %21, -542963121
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%23 = icmp ult i32 %22, undef
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br i1 undef, label %16, label %24
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; <label>:24 ; preds = %16, %15, %10, %5, %4, %3, %2, %1, %0
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ret void
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}
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