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Exit with nice warnings when register allocator run out of registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63267 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -377,6 +377,10 @@ namespace llvm {
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const int *RHSValNoAssignments,
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SmallVector<VNInfo*, 16> &NewVNInfo);
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/// isInOneLiveRange - Return true if the range specified is entirely in the
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/// a single LiveRange of the live interval.
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bool isInOneLiveRange(unsigned Start, unsigned End);
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/// removeRange - Remove the specified range from this interval. Note that
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/// the range must be a single LiveRange in its entirety.
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void removeRange(unsigned Start, unsigned End, bool RemoveDeadValNo = false);
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@ -244,6 +244,16 @@ LiveInterval::addRangeFrom(LiveRange LR, iterator From) {
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return ranges.insert(it, LR);
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}
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/// isInOneLiveRange - Return true if the range specified is entirely in the
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/// a single LiveRange of the live interval.
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bool LiveInterval::isInOneLiveRange(unsigned Start, unsigned End) {
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Ranges::iterator I = std::upper_bound(ranges.begin(), ranges.end(), Start);
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if (I == ranges.begin())
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return false;
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--I;
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return I->contains(Start) && I->contains(End-1);
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}
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/// removeRange - Remove the specified range from this interval. Note that
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/// the range must be in a single LiveRange in its entirety.
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@ -2228,7 +2228,19 @@ void LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li,
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unsigned Index = getInstructionIndex(MI);
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if (pli.liveAt(Index)) {
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vrm.addEmergencySpill(SpillReg, MI);
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pli.removeRange(getLoadIndex(Index), getStoreIndex(Index)+1);
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unsigned StartIdx = getLoadIndex(Index);
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unsigned EndIdx = getStoreIndex(Index)+1;
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if (pli.isInOneLiveRange(StartIdx, EndIdx))
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pli.removeRange(StartIdx, EndIdx);
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else {
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cerr << "Ran out of registers during register allocation!\n";
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if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
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cerr << "Please check your inline asm statement for invalid "
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<< "constraints:\n";
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MI->print(cerr.stream(), tm_);
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}
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exit(1);
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}
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for (const unsigned* AS = tri_->getSubRegisters(SpillReg); *AS; ++AS) {
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if (!hasInterval(*AS))
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continue;
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@ -27,6 +27,7 @@
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#include "llvm/Support/Compiler.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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@ -237,7 +238,7 @@ namespace {
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/// value. This method returns the modified instruction.
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///
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MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned OpNum);
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unsigned OpNum, SmallSet<unsigned, 4> &RRegs);
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/// ComputeLocalLiveness - Computes liveness of registers within a basic
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/// block, setting the killed/dead flags as appropriate.
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@ -475,7 +476,8 @@ unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
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/// modified instruction.
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///
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MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned OpNum) {
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unsigned OpNum,
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SmallSet<unsigned, 4> &ReloadedRegs) {
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unsigned VirtReg = MI->getOperand(OpNum).getReg();
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// If the virtual register is already available, just update the instruction
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@ -513,6 +515,29 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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MF->getRegInfo().setPhysRegUsed(PhysReg);
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MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
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getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
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if (!ReloadedRegs.insert(PhysReg)) {
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cerr << "Ran out of registers during register allocation!\n";
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if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
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cerr << "Please check your inline asm statement for invalid "
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<< "constraints:\n";
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MI->print(cerr.stream(), TM);
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}
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exit(1);
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}
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for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
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*SubRegs; ++SubRegs) {
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if (!ReloadedRegs.insert(*SubRegs)) {
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cerr << "Ran out of registers during register allocation!\n";
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if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
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cerr << "Please check your inline asm statement for invalid "
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<< "constraints:\n";
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MI->print(cerr.stream(), TM);
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}
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exit(1);
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}
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}
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return MI;
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}
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@ -581,17 +606,16 @@ void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
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if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
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const unsigned* subregs = TRI->getAliasSet(MO.getReg());
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if (subregs) {
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while (*subregs) {
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const unsigned* Aliases = TRI->getAliasSet(MO.getReg());
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if (Aliases) {
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while (*Aliases) {
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DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
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alias = LastUseDef.find(*subregs);
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alias = LastUseDef.find(*Aliases);
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if (alias != LastUseDef.end() &&
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alias->second.first != I)
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LastUseDef[*subregs] = std::make_pair(I, i);
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if (alias != LastUseDef.end() && alias->second.first != I)
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LastUseDef[*Aliases] = std::make_pair(I, i);
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++subregs;
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++Aliases;
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}
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}
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}
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@ -695,12 +719,12 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
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MF->getRegInfo().setPhysRegUsed(Reg);
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PhysRegsUsed[Reg] = 0; // It is free and reserved now
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AddToPhysRegsUseOrder(Reg);
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for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
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*AliasSet; ++AliasSet) {
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if (PhysRegsUsed[*AliasSet] != -2) {
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AddToPhysRegsUseOrder(*AliasSet);
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PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
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MF->getRegInfo().setPhysRegUsed(*AliasSet);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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*SubRegs; ++SubRegs) {
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if (PhysRegsUsed[*SubRegs] != -2) {
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AddToPhysRegsUseOrder(*SubRegs);
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PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
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MF->getRegInfo().setPhysRegUsed(*SubRegs);
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}
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}
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}
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@ -778,12 +802,12 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
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PhysRegsUsed[Reg] = 0; // It is free and reserved now
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AddToPhysRegsUseOrder(Reg);
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for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
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*AliasSet; ++AliasSet) {
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if (PhysRegsUsed[*AliasSet] != -2) {
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MF->getRegInfo().setPhysRegUsed(*AliasSet);
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PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
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AddToPhysRegsUseOrder(*AliasSet);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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*SubRegs; ++SubRegs) {
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if (PhysRegsUsed[*SubRegs] != -2) {
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MF->getRegInfo().setPhysRegUsed(*SubRegs);
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PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
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AddToPhysRegsUseOrder(*SubRegs);
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}
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}
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}
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@ -797,12 +821,13 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
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// physical register is referenced by the instruction, that it is guaranteed
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// to be live-in, or the input is badly hosed.
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//
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SmallSet<unsigned, 4> ReloadedRegs;
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for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
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MachineOperand& MO = MI->getOperand(i);
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// here we are looking for only used operands (never def&use)
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if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
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TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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MI = reloadVirtReg(MBB, MI, i);
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MI = reloadVirtReg(MBB, MI, i, ReloadedRegs);
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}
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// If this instruction is the last user of this register, kill the
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@ -830,13 +855,13 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
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DOUT << " Last use of " << TRI->getName(PhysReg)
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<< "[%reg" << VirtReg <<"], removing it from live set\n";
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removePhysReg(PhysReg);
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for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
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*AliasSet; ++AliasSet) {
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if (PhysRegsUsed[*AliasSet] != -2) {
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for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
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*SubRegs; ++SubRegs) {
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if (PhysRegsUsed[*SubRegs] != -2) {
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DOUT << " Last use of "
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<< TRI->getName(*AliasSet)
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<< TRI->getName(*SubRegs)
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<< "[%reg" << VirtReg <<"], removing it from live set\n";
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removePhysReg(*AliasSet);
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removePhysReg(*SubRegs);
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}
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}
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}
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@ -861,12 +886,12 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
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PhysRegsUsed[Reg] = 0; // It is free and reserved now
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AddToPhysRegsUseOrder(Reg);
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for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
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*AliasSet; ++AliasSet) {
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if (PhysRegsUsed[*AliasSet] != -2) {
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MF->getRegInfo().setPhysRegUsed(*AliasSet);
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PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
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AddToPhysRegsUseOrder(*AliasSet);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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*SubRegs; ++SubRegs) {
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if (PhysRegsUsed[*SubRegs] != -2) {
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MF->getRegInfo().setPhysRegUsed(*SubRegs);
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PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
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AddToPhysRegsUseOrder(*SubRegs);
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}
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}
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}
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@ -883,12 +908,12 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
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PhysRegsUsed[Reg] = 0; // It is free and reserved now
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}
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MF->getRegInfo().setPhysRegUsed(Reg);
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for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
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*AliasSet; ++AliasSet) {
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if (PhysRegsUsed[*AliasSet] != -2) {
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AddToPhysRegsUseOrder(*AliasSet);
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PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
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MF->getRegInfo().setPhysRegUsed(*AliasSet);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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*SubRegs; ++SubRegs) {
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if (PhysRegsUsed[*SubRegs] != -2) {
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AddToPhysRegsUseOrder(*SubRegs);
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PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
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MF->getRegInfo().setPhysRegUsed(*SubRegs);
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}
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}
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}
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32
test/CodeGen/X86/illegal-asm.ll
Normal file
32
test/CodeGen/X86/illegal-asm.ll
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@ -0,0 +1,32 @@
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; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -disable-fp-elim
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; XFAIL: *
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; Expected to run out of registers during allocation.
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; rdar://6251720
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%struct.CABACContext = type { i32, i32, i8* }
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%struct.H264Context = type { %struct.CABACContext, [460 x i8] }
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@coeff_abs_level_m1_offset = common global [6 x i32] zeroinitializer ; <[6 x i32]*> [#uses=1]
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@coeff_abs_level1_ctx = common global [8 x i8] zeroinitializer ; <[8 x i8]*> [#uses=1]
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define i32 @decode_cabac_residual(%struct.H264Context* %h, i32 %cat) nounwind {
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entry:
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%0 = getelementptr [6 x i32]* @coeff_abs_level_m1_offset, i32 0, i32 %cat ; <i32*> [#uses=1]
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%1 = load i32* %0, align 4 ; <i32> [#uses=1]
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%2 = load i8* getelementptr ([8 x i8]* @coeff_abs_level1_ctx, i32 0, i32 0), align 1 ; <i8> [#uses=1]
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%3 = zext i8 %2 to i32 ; <i32> [#uses=1]
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%.sum = add i32 %3, %1 ; <i32> [#uses=1]
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%4 = getelementptr %struct.H264Context* %h, i32 0, i32 1, i32 %.sum ; <i8*> [#uses=2]
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%5 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 0 ; <i32*> [#uses=2]
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%6 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 1 ; <i32*> [#uses=2]
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%7 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 2 ; <i8**> [#uses=2]
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%8 = load i32* %5, align 4 ; <i32> [#uses=1]
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%9 = load i32* %6, align 4 ; <i32> [#uses=1]
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%10 = load i8* %4, align 4 ; <i8> [#uses=1]
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%asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#$0 $1 $2 $3 $4 $5", "=&{di},=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %7, i8* %4, i32 %8, i32 %9, i8** %7, i8 %10) nounwind ; <{ i32, i32, i32, i32 }> [#uses=3]
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%asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0 ; <i32> [#uses=1]
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%asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1 ; <i32> [#uses=1]
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store i32 %asmresult1, i32* %5
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%asmresult2 = extractvalue { i32, i32, i32, i32 } %asmtmp, 2 ; <i32> [#uses=1]
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store i32 %asmresult2, i32* %6
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ret i32 %asmresult
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}
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