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Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-10-07 01:50:48 +00:00
parent b046810fe4
commit 5a50ceeaea
7 changed files with 143 additions and 42 deletions
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6
lib/Target/ARM/ARMSchedule.td
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@@ -120,10 +120,12 @@ def IIC_fpSQRT32 : InstrItinClass;
def IIC_fpSQRT64 : InstrItinClass;
def IIC_fpLoad32 : InstrItinClass;
def IIC_fpLoad64 : InstrItinClass;
def IIC_fpLoadm : InstrItinClass<0>; // micro-coded
def IIC_fpLoad_m : InstrItinClass<0>; // micro-coded
def IIC_fpLoad_mu : InstrItinClass<0>; // micro-coded
def IIC_fpStore32 : InstrItinClass;
def IIC_fpStore64 : InstrItinClass;
def IIC_fpStorem : InstrItinClass<0>; // micro-coded
def IIC_fpStore_m : InstrItinClass<0>; // micro-coded
def IIC_fpStore_mu : InstrItinClass<0>; // micro-coded
def IIC_VLD1 : InstrItinClass;
def IIC_VLD2 : InstrItinClass;
def IIC_VLD3 : InstrItinClass;