6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-28 06:32:09 +00:00
Code Issues Projects Releases Wiki Activity

Make more use of is128BitVector/is256BitVector in place of getSizeInBits() == 128/256.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172792 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2013-01-18 06:44:29 +00:00
parent 081c29b256
commit 5a529e4f86
1 changed files with 31 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

66
lib/Target/X86/X86ISelLowering.cpp
View File

@ -3361,8 +3361,8 @@ static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
/// is suitable for input to PALIGNR. /// is suitable for input to PALIGNR.
static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
const X86Subtarget *Subtarget) { const X86Subtarget *Subtarget) {
if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) || if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
(VT.getSizeInBits() == 256 && !Subtarget->hasInt256())) (VT.is256BitVector() && !Subtarget->hasInt256()))
return false; return false;
unsigned NumElts = VT.getVectorNumElements(); unsigned NumElts = VT.getVectorNumElements();
@ -3451,7 +3451,7 @@ static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
/// reverse of what x86 shuffles want. /// reverse of what x86 shuffles want.
static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256, static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256,
bool Commuted = false) { bool Commuted = false) {
if (!HasFp256 && VT.getSizeInBits() == 256) if (!HasFp256 && VT.is256BitVector())
return false; return false;
unsigned NumElems = VT.getVectorNumElements(); unsigned NumElems = VT.getVectorNumElements();
@ -3636,7 +3636,7 @@ static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
assert((VT.is128BitVector() || VT.is256BitVector()) && assert((VT.is128BitVector() || VT.is256BitVector()) &&
"Unsupported vector type for unpckh"); "Unsupported vector type for unpckh");
if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
(!HasInt256 || (NumElts != 16 && NumElts != 32))) (!HasInt256 || (NumElts != 16 && NumElts != 32)))
return false; return false;
@ -3675,7 +3675,7 @@ static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
assert((VT.is128BitVector() || VT.is256BitVector()) && assert((VT.is128BitVector() || VT.is256BitVector()) &&
"Unsupported vector type for unpckh"); "Unsupported vector type for unpckh");
if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
(!HasInt256 || (NumElts != 16 && NumElts != 32))) (!HasInt256 || (NumElts != 16 && NumElts != 32)))
return false; return false;
@ -3706,14 +3706,14 @@ static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
/// <0, 0, 1, 1> /// <0, 0, 1, 1>
static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
bool HasInt256) {
unsigned NumElts = VT.getVectorNumElements(); unsigned NumElts = VT.getVectorNumElements();
bool Is256BitVec = VT.is256BitVector();
assert((VT.is128BitVector() || VT.is256BitVector()) && assert((VT.is128BitVector() || VT.is256BitVector()) &&
"Unsupported vector type for unpckh"); "Unsupported vector type for unpckh");
if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
(!HasInt256 || (NumElts != 16 && NumElts != 32))) (!HasInt256 || (NumElts != 16 && NumElts != 32)))
return false; return false;
@ -3721,7 +3721,7 @@ static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
// FIXME: Need a better way to get rid of this, there's no latency difference // FIXME: Need a better way to get rid of this, there's no latency difference
// between UNPCKLPD and MOVDDUP, the later should always be checked first and // between UNPCKLPD and MOVDDUP, the later should always be checked first and
// the former later. We should also remove the "_undef" special mask. // the former later. We should also remove the "_undef" special mask.
if (NumElts == 4 && VT.getSizeInBits() == 256) if (NumElts == 4 && Is256BitVec)
return false; return false;
// Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
@ -3755,7 +3755,7 @@ static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
assert((VT.is128BitVector() || VT.is256BitVector()) && assert((VT.is128BitVector() || VT.is256BitVector()) &&
"Unsupported vector type for unpckh"); "Unsupported vector type for unpckh");
if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
(!HasInt256 || (NumElts != 16 && NumElts != 32))) (!HasInt256 || (NumElts != 16 && NumElts != 32)))
return false; return false;
@ -3871,7 +3871,7 @@ static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
unsigned NumElts = VT.getVectorNumElements(); unsigned NumElts = VT.getVectorNumElements();
// Only match 256-bit with 32/64-bit types // Only match 256-bit with 32/64-bit types
if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) if (!VT.is256BitVector() || (NumElts != 4 && NumElts != 8))
return false; return false;
unsigned NumLanes = VT.getSizeInBits()/128; unsigned NumLanes = VT.getSizeInBits()/128;
@ -3927,8 +3927,8 @@ static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
unsigned NumElems = VT.getVectorNumElements(); unsigned NumElems = VT.getVectorNumElements();
if ((VT.getSizeInBits() == 128 && NumElems != 4) || if ((VT.is128BitVector() && NumElems != 4) ||
(VT.getSizeInBits() == 256 && NumElems != 8)) (VT.is256BitVector() && NumElems != 8))
return false; return false;
// "i+1" is the value the indexed mask element must have // "i+1" is the value the indexed mask element must have
@ -3950,8 +3950,8 @@ static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
unsigned NumElems = VT.getVectorNumElements(); unsigned NumElems = VT.getVectorNumElements();
if ((VT.getSizeInBits() == 128 && NumElems != 4) || if ((VT.is128BitVector() && NumElems != 4) ||
(VT.getSizeInBits() == 256 && NumElems != 8)) (VT.is256BitVector() && NumElems != 8))
return false; return false;
// "i" is the value the indexed mask element must have // "i" is the value the indexed mask element must have
@ -4358,12 +4358,11 @@ static bool isZeroShuffle(ShuffleVectorSDNode *N) {
static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
SelectionDAG &DAG, DebugLoc dl) { SelectionDAG &DAG, DebugLoc dl) {
assert(VT.isVector() && "Expected a vector type"); assert(VT.isVector() && "Expected a vector type");
unsigned Size = VT.getSizeInBits();
// Always build SSE zero vectors as <4 x i32> bitcasted // Always build SSE zero vectors as <4 x i32> bitcasted
// to their dest type. This ensures they get CSE'd. // to their dest type. This ensures they get CSE'd.
SDValue Vec; SDValue Vec;
if (Size == 128) { // SSE if (VT.is128BitVector()) { // SSE
if (Subtarget->hasSSE2()) { // SSE2 if (Subtarget->hasSSE2()) { // SSE2
SDValue Cst = DAG.getTargetConstant(0, MVT::i32); SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
@ -4371,7 +4370,7 @@ static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
} }
} else if (Size == 256) { // AVX } else if (VT.is256BitVector()) { // AVX
if (Subtarget->hasInt256()) { // AVX2 if (Subtarget->hasInt256()) { // AVX2
SDValue Cst = DAG.getTargetConstant(0, MVT::i32); SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
@ -4396,11 +4395,10 @@ static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
static SDValue getOnesVector(EVT VT, bool HasInt256, SelectionDAG &DAG, static SDValue getOnesVector(EVT VT, bool HasInt256, SelectionDAG &DAG,
DebugLoc dl) { DebugLoc dl) {
assert(VT.isVector() && "Expected a vector type"); assert(VT.isVector() && "Expected a vector type");
unsigned Size = VT.getSizeInBits();
SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
SDValue Vec; SDValue Vec;
if (Size == 256) { if (VT.is256BitVector()) {
if (HasInt256) { // AVX2 if (HasInt256) { // AVX2
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
@ -4408,7 +4406,7 @@ static SDValue getOnesVector(EVT VT, bool HasInt256, SelectionDAG &DAG,
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl); Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
} }
} else if (Size == 128) { } else if (VT.is128BitVector()) {
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
} else } else
llvm_unreachable("Unexpected vector type"); llvm_unreachable("Unexpected vector type");
@ -4487,14 +4485,13 @@ static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
EVT VT = V.getValueType(); EVT VT = V.getValueType();
DebugLoc dl = V.getDebugLoc(); DebugLoc dl = V.getDebugLoc();
unsigned Size = VT.getSizeInBits();
if (Size == 128) { if (VT.is128BitVector()) {
V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
&SplatMask[0]); &SplatMask[0]);
} else if (Size == 256) { } else if (VT.is256BitVector()) {
// To use VPERMILPS to splat scalars, the second half of indicies must // To use VPERMILPS to splat scalars, the second half of indicies must
// refer to the higher part, which is a duplication of the lower one, // refer to the higher part, which is a duplication of the lower one,
// because VPERMILPS can only handle in-lane permutations. // because VPERMILPS can only handle in-lane permutations.
@ -4518,14 +4515,14 @@ static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
int EltNo = SV->getSplatIndex(); int EltNo = SV->getSplatIndex();
int NumElems = SrcVT.getVectorNumElements(); int NumElems = SrcVT.getVectorNumElements();
unsigned Size = SrcVT.getSizeInBits(); bool Is256BitVec = SrcVT.is256BitVector();
assert(((Size == 128 && NumElems > 4) || Size == 256) && assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
"Unknown how to promote splat for type"); "Unknown how to promote splat for type");
// Extract the 128-bit part containing the splat element and update // Extract the 128-bit part containing the splat element and update
// the splat element index when it refers to the higher register. // the splat element index when it refers to the higher register.
if (Size == 256) { if (Is256BitVec) {
V1 = Extract128BitVector(V1, EltNo, DAG, dl); V1 = Extract128BitVector(V1, EltNo, DAG, dl);
if (EltNo >= NumElems/2) if (EltNo >= NumElems/2)
EltNo -= NumElems/2; EltNo -= NumElems/2;
@ -4542,7 +4539,7 @@ static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
// Recreate the 256-bit vector and place the same 128-bit vector // Recreate the 256-bit vector and place the same 128-bit vector
// into the low and high part. This is necessary because we want // into the low and high part. This is necessary because we want
// to use VPERM* to shuffle the vectors // to use VPERM* to shuffle the vectors
if (Size == 256) { if (Is256BitVec) {
V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1); V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
} }
@ -6672,7 +6669,6 @@ X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
// Handle splat operations // Handle splat operations
if (SVOp->isSplat()) { if (SVOp->isSplat()) {
unsigned NumElem = VT.getVectorNumElements(); unsigned NumElem = VT.getVectorNumElements();
int Size = VT.getSizeInBits();
// Use vbroadcast whenever the splat comes from a foldable load // Use vbroadcast whenever the splat comes from a foldable load
SDValue Broadcast = LowerVectorBroadcast(Op, DAG); SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
@ -6680,8 +6676,8 @@ X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
return Broadcast; return Broadcast;
// Handle splats by matching through known shuffle masks // Handle splats by matching through known shuffle masks
if ((Size == 128 && NumElem <= 4) || if ((VT.is128BitVector() && NumElem <= 4) ||
(Size == 256 && NumElem <= 8)) (VT.is256BitVector() && NumElem <= 8))
return SDValue(); return SDValue();
// All remaning splats are promoted to target supported vector shuffles. // All remaning splats are promoted to target supported vector shuffles.
@ -15970,7 +15966,7 @@ static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget *Subtarget) { const X86Subtarget *Subtarget) {
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
if (VT.getSizeInBits() != 256) if (!VT.is256BitVector())
return SDValue(); return SDValue();
assert((N->getOpcode() == ISD::ANY_EXTEND || assert((N->getOpcode() == ISD::ANY_EXTEND ||
@ -15979,7 +15975,7 @@ static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
SDValue Narrow = N->getOperand(0); SDValue Narrow = N->getOperand(0);
EVT NarrowVT = Narrow->getValueType(0); EVT NarrowVT = Narrow->getValueType(0);
if (NarrowVT.getSizeInBits() != 128) if (!NarrowVT.is128BitVector())
return SDValue(); return SDValue();
if (Narrow->getOpcode() != ISD::XOR && if (Narrow->getOpcode() != ISD::XOR &&
@ -17075,7 +17071,7 @@ static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
} }
} }
if (VT.isVector() && VT.getSizeInBits() == 256) { if (VT.is256BitVector()) {
SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget); SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
if (R.getNode()) if (R.getNode())
return R; return R;