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aesthetic changes, no functionality change. Evan, it's not clear
what 'Available' is, please add a comment near it and rename it if appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44703 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -562,7 +562,7 @@ void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
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/// MatchAddress - Add the specified node to the specified addressing mode,
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/// returning true if it cannot be done. This just pattern matches for the
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/// addressing mode
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/// addressing mode.
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bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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bool isRoot, unsigned Depth) {
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// Limit recursion.
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@ -653,33 +653,35 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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break;
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case ISD::SHL:
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if (!Available && AM.IndexReg.Val == 0 && AM.Scale == 1)
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
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unsigned Val = CN->getValue();
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if (Val == 1 || Val == 2 || Val == 3) {
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AM.Scale = 1 << Val;
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SDOperand ShVal = N.Val->getOperand(0);
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if (Available || AM.IndexReg.Val != 0 || AM.Scale != 1)
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break;
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
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unsigned Val = CN->getValue();
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if (Val == 1 || Val == 2 || Val == 3) {
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AM.Scale = 1 << Val;
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SDOperand ShVal = N.Val->getOperand(0);
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// Okay, we know that we have a scale by now. However, if the scaled
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// value is an add of something and a constant, we can fold the
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// constant into the disp field here.
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if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
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isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
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AM.IndexReg = ShVal.Val->getOperand(0);
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ConstantSDNode *AddVal =
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cast<ConstantSDNode>(ShVal.Val->getOperand(1));
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uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
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if (isInt32(Disp))
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AM.Disp = Disp;
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else
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AM.IndexReg = ShVal;
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} else {
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// Okay, we know that we have a scale by now. However, if the scaled
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// value is an add of something and a constant, we can fold the
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// constant into the disp field here.
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if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
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isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
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AM.IndexReg = ShVal.Val->getOperand(0);
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ConstantSDNode *AddVal =
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cast<ConstantSDNode>(ShVal.Val->getOperand(1));
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uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
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if (isInt32(Disp))
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AM.Disp = Disp;
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else
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AM.IndexReg = ShVal;
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}
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return false;
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} else {
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AM.IndexReg = ShVal;
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}
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return false;
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}
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break;
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}
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case ISD::SMUL_LOHI:
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case ISD::UMUL_LOHI:
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@ -738,22 +740,22 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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case ISD::OR:
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// Handle "X | C" as "X + C" iff X is known to have C bits clear.
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if (!Available) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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X86ISelAddressMode Backup = AM;
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// Start with the LHS as an addr mode.
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if (!MatchAddress(N.getOperand(0), AM, false) &&
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// Address could not have picked a GV address for the displacement.
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AM.GV == NULL &&
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// On x86-64, the resultant disp must fit in 32-bits.
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isInt32(AM.Disp + CN->getSignExtended()) &&
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// Check to see if the LHS & C is zero.
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CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getValue())) {
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AM.Disp += CN->getValue();
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return false;
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}
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AM = Backup;
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if (Available) break;
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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X86ISelAddressMode Backup = AM;
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// Start with the LHS as an addr mode.
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if (!MatchAddress(N.getOperand(0), AM, false) &&
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// Address could not have picked a GV address for the displacement.
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AM.GV == NULL &&
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// On x86-64, the resultant disp must fit in 32-bits.
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isInt32(AM.Disp + CN->getSignExtended()) &&
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// Check to see if the LHS & C is zero.
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CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getValue())) {
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AM.Disp += CN->getValue();
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return false;
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}
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AM = Backup;
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}
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break;
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}
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