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Expand the repertoire of the forms we can print and encode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11537 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -699,17 +699,16 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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//
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
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(MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
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isMem(MI, 2))
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(MI->getNumOperands() == 2+4 && MI->getOperand(5).isImmediate() && isMem(MI, 1))
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&& "Bad format for MRMSrcMem!");
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if (MI->getNumOperands() == 2+4 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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O << ", " << sizePtr(Desc) << " ";
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printMemReference(MI, MI->getNumOperands()-4);
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printMemReference(MI, 1);
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if (MI->getNumOperands() == 2+4) {
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O << ", ";
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printOp(MI->getOperand(5));
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}
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O << "\n";
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return;
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}
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@ -699,17 +699,16 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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//
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
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(MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
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isMem(MI, 2))
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(MI->getNumOperands() == 2+4 && MI->getOperand(5).isImmediate() && isMem(MI, 1))
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&& "Bad format for MRMSrcMem!");
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if (MI->getNumOperands() == 2+4 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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O << ", " << sizePtr(Desc) << " ";
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printMemReference(MI, MI->getNumOperands()-4);
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printMemReference(MI, 1);
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if (MI->getNumOperands() == 2+4) {
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O << ", ";
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printOp(MI->getOperand(5));
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}
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O << "\n";
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return;
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}
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@ -574,8 +574,9 @@ void Emitter::emitInstruction(MachineInstr &MI) {
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case X86II::MRMSrcMem:
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MCE.emitByte(BaseOpcode);
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emitMemModRMByte(MI, MI.getNumOperands()-4,
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getX86RegNum(MI.getOperand(0).getReg()));
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emitMemModRMByte(MI, 1, getX86RegNum(MI.getOperand(0).getReg()));
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if (MI.getNumOperands() == 2+4)
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emitConstant(MI.getOperand(5).getImmedValue(), sizeOfPtr(Desc));
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break;
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case X86II::MRMS0r: case X86II::MRMS1r:
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