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Fix PR3210: Detect more Intel processors. Patch by Torok Edwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61602 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -11,10 +11,12 @@
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "subtarget"
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#include "X86Subtarget.h"
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#include "X86GenSubtarget.inc"
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#include "llvm/Module.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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@ -236,15 +238,23 @@ static const char *GetCurrentX86CPU() {
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case 9:
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case 13: return "pentium-m";
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case 14: return "yonah";
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case 15: return "core2";
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case 23: return "penryn";
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case 15:
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case 22: // Celeron M 540
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return "core2";
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case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE)
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return "penryn";
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default: return "i686";
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}
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case 15: {
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switch (Model) {
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case 3:
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case 4:
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case 6: // same as 4, but 65nm
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return (Em64T) ? "nocona" : "prescott";
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case 28:
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// Intel Atom, and Core i7 both have this model.
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// Atom has SSSE3, Core i7 has SSE4.2
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return "core2";
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default:
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return (Em64T) ? "x86-64" : "pentium4";
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}
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@ -324,6 +334,9 @@ X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
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if (X86SSELevel < SSE2)
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X86SSELevel = SSE2;
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}
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DOUT << "Subtarget features: SSELevel " << X86SSELevel
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<< ", 3DNowLevel " << X863DNowLevel
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<< ", 64bit " << HasX86_64 << "\n";
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// Set the boolean corresponding to the current target triple, or the default
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// if one cannot be determined, to true.
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