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Work around an interaction between fast-isel and regalloc=local. The

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local register allocator's physreg liveness doesn't recognize subregs,
so it doesn't know that defs of %ecx that are immediately followed by
uses of %cl aren't dead. This comes up due to the way fast-isel emits
shift instructions.

This is a temporary workaround. Arguably, local regalloc should
handle subreg references correctly. On the other hand, perhaps
fast-isel should use INSERT_SUBREG instead of just assigning to the
most convenient super-register of %cl when lowering shifts.

This fixes MultiSource/Benchmarks/MallocBench/espresso,
MultiSource/Applications/hexxagon, and others, under -fast.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56947 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-10-02 14:56:12 +00:00
parent 5e249b4a14
commit 5bbee4b40a
1 changed files with 5 additions and 1 deletions
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6
lib/Target/X86/X86FastISel.cpp
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@ -741,7 +741,11 @@ bool X86FastISel::X86SelectShift(Instruction *I) {
if (Op1Reg == 0) return false;
TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
unsigned ResultReg = createResultReg(RC);
BuildMI(MBB, TII.get(OpReg), ResultReg).addReg(Op0Reg);
BuildMI(MBB, TII.get(OpReg), ResultReg).addReg(Op0Reg)
// FIXME: The "Local" register allocator's physreg liveness doesn't
// recognize subregs. Adding the superreg of CL that's actually defined
// prevents it from being re-allocated for this instruction.
.addReg(CReg, false, true);
UpdateValueMap(I, ResultReg);
return true;
}