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The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Silviu Baranga 2012-03-20 15:54:56 +00:00
parent 8da7a4668f
commit 5c062ad926
7 changed files with 27 additions and 9 deletions
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4
lib/Target/ARM/ARMInstrInfo.td
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@ -4128,8 +4128,8 @@ multiclass AsI1_bincc_irs<bits<4> opcod, string opc,
let Inst{3-0} = shift{3-0}; let Inst{3-0} = shift{3-0};
} }
def rsr : AsI1<opcod, (outs GPR:$Rd), def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
(ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
iis, opc, "\t$Rd, $Rn, $shift", []>, iis, opc, "\t$Rd, $Rn, $shift", []>,
RegConstraint<"$Rn = $Rd"> { RegConstraint<"$Rn = $Rd"> {
bits<4> Rd; bits<4> Rd;

10
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -869,8 +869,14 @@ static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
static DecodeStatus static DecodeStatus
DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if (RegNo == 15) return MCDisassembler::Fail; DecodeStatus S = MCDisassembler::Success;
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
if (RegNo == 15)
S = MCDisassembler::SoftFail;
Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
return S;
} }
static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,

4
test/MC/Disassembler/ARM/invalid-LSL-regform.txt → test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt
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@ -1,4 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ -8,4 +8,6 @@
# #
# A8.6.89 LSL (register) # A8.6.89 LSL (register)
# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
# CHECK: warning: potentially undefined instruction encoding
0x12 0xf1 0xa0 0xe1 0x12 0xf1 0xa0 0xe1

4
test/MC/Disassembler/ARM/invalid-RSC-arm.txt → test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt
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@ -1,4 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
# Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5) # Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ -6,4 +6,6 @@
# | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| # | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; # if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
# CHECK: warning: potentially undefined instruction encoding
0x5f 0xf8 0xe4 0x30 0x5f 0xf8 0xe4 0x30

4
test/MC/Disassembler/ARM/invalid-SSAT-arm.txt → test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt
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@ -1,4 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
# Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13) # Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ -8,4 +8,6 @@
# #
# A8.6.183 SSAT # A8.6.183 SSAT
# if d == 15 || n == 15 then UNPREDICTABLE; # if d == 15 || n == 15 then UNPREDICTABLE;
# CHECK:warning: potentially undefined instruction encoding
0x1a 0xf4 0xa0 0xe6 0x1a 0xf4 0xa0 0xe6

4
test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt → test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt
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@ -1,4 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
# Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7) # Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ -7,4 +7,6 @@
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# #
# if t == 15 then UNPREDICTABLE # if t == 15 then UNPREDICTABLE
# CHECK: warning: potentially undefined instruction encoding
0x00 0xf0 0xcf 0xe7 0x00 0xf0 0xcf 0xe7

6
test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt → test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt
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@ -1,4 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
# Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4) # Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ -10,3 +10,7 @@
# #
# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
0x9f 0x5f 0x66 0xe6 0x9f 0x5f 0x66 0xe6
# CHECK: warning: potentially undefined
# CHECK: uqadd8 r5, r6, pc