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The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4128,8 +4128,8 @@ multiclass AsI1_bincc_irs<bits<4> opcod, string opc,
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let Inst{3-0} = shift{3-0};
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}
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def rsr : AsI1<opcod, (outs GPR:$Rd),
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(ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
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def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
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(ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
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iis, opc, "\t$Rd, $Rn, $shift", []>,
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RegConstraint<"$Rn = $Rd"> {
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bits<4> Rd;
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@ -869,8 +869,14 @@ static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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static DecodeStatus
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DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo == 15) return MCDisassembler::Fail;
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return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
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DecodeStatus S = MCDisassembler::Success;
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if (RegNo == 15)
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S = MCDisassembler::SoftFail;
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Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
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return S;
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}
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static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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@ -1,4 +1,4 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
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# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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@ -8,4 +8,6 @@
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#
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# A8.6.89 LSL (register)
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# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
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# CHECK: warning: potentially undefined instruction encoding
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0x12 0xf1 0xa0 0xe1
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@ -1,4 +1,4 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
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# Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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@ -6,4 +6,6 @@
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# | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
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# -------------------------------------------------------------------------------------------------
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# if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
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# CHECK: warning: potentially undefined instruction encoding
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0x5f 0xf8 0xe4 0x30
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@ -1,4 +1,4 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
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# Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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@ -8,4 +8,6 @@
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#
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# A8.6.183 SSAT
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# if d == 15 || n == 15 then UNPREDICTABLE;
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# CHECK:warning: potentially undefined instruction encoding
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0x1a 0xf4 0xa0 0xe6
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@ -1,4 +1,4 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
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# Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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@ -7,4 +7,6 @@
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# -------------------------------------------------------------------------------------------------
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#
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# if t == 15 then UNPREDICTABLE
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# CHECK: warning: potentially undefined instruction encoding
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0x00 0xf0 0xcf 0xe7
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@ -1,4 +1,4 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
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# Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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@ -10,3 +10,7 @@
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#
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# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
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0x9f 0x5f 0x66 0xe6
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# CHECK: warning: potentially undefined
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# CHECK: uqadd8 r5, r6, pc
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