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Change the SREM case to match the logic in the IR version ComputeMaskedBits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94805 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1925,19 +1925,28 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
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}
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case ISD::SREM:
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if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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const APInt &RA = Rem->getAPIntValue();
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if (RA.isPowerOf2() || (-RA).isPowerOf2()) {
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APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA;
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const APInt &RA = Rem->getAPIntValue().abs();
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if (RA.isPowerOf2()) {
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APInt LowBits = RA - 1;
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APInt Mask2 = LowBits | APInt::getSignBit(BitWidth);
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ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1);
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// If the sign bit of the first operand is zero, the sign bit of
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// the result is zero. If the first operand has no one bits below
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// the second operand's single 1 bit, its sign will be zero.
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if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits))
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KnownZero2 |= ~LowBits;
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// The low bits of the first operand are unchanged by the srem.
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KnownZero = KnownZero2 & LowBits;
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KnownOne = KnownOne2 & LowBits;
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KnownZero |= KnownZero2 & Mask;
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// If the first operand is non-negative or has all low bits zero, then
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// the upper bits are all zero.
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if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits))
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KnownZero |= ~LowBits;
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// If the first operand is negative and not all low bits are zero, then
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// the upper bits are all one.
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if (KnownOne2[BitWidth-1] && ((KnownOne2 & LowBits) != 0))
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KnownOne |= ~LowBits;
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KnownZero &= Mask;
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KnownOne &= Mask;
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assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
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}
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