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Fix PR 10635. When generating integer constants, the constant element type may

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be illegal, even if the requested vector type is legal. Testcase is one of the
disabled ARM tests in the vector-select patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137562 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem 2011-08-13 20:31:45 +00:00
parent 9a0f436da2
commit 5cbba01671
1 changed files with 7 additions and 0 deletions
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7
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -928,6 +928,13 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT) {
assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
"APInt size does not match type size!");
// In some cases the vector type is legal but the element type is illegal.
// In this case, promote the inserted value. The type does not need to match
// the vector element type. Any extra bits introduced will be
// truncated away.
if (VT.isVector())
EltVT = TLI.getTypeToTransformTo(*getContext(), EltVT);
unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);