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cell really does support cross-regclass moves, because R3 is in lots of different regclasses, and the code is not consistent when it comes to value tracking.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48119 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-03-09 20:31:11 +00:00
parent 68a0d0984d
commit 5e09da236e
1 changed files with 9 additions and 4 deletions
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13
lib/Target/CellSPU/SPUInstrInfo.cpp
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@ -186,10 +186,15 @@ void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const
{
if (DestRC != SrcRC) {
cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
abort();
}
// We support cross register class moves for our aliases, such as R3 in any
// reg class to any other reg class containing R3. This is required because
// we instruction select bitconvert i64 -> f64 as a noop for example, so our
// types have no specific meaning.
//if (DestRC != SrcRC) {
// cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
// abort();
//}
if (DestRC == SPU::R8CRegisterClass) {
BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);