6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-09 01:38:03 +00:00
Code Issues Projects Releases Wiki Activity

[FastISel][AArch64] Also allow folding of sign-/zero-extend and logical

Browse Source 
shift-right for booleans (i1).

Logical shift-right immediate with sign-/zero-extensions also works for boolean
values.  Update the assert and the test cases to reflect that fact.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222270 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2014-11-18 22:38:42 +00:00
parent d3635f07ed
commit 5e3288f85b
2 changed files with 46 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/AArch64/AArch64FastISel.cpp
View File

@ -3996,8 +3996,9 @@ unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
bool IsZExt) {
assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
"Unexpected source/return type pair.");
assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
SrcVT == MVT::i64) && "Unexpected source value type.");
assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
"Unexpected source value type.");
assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
RetVT == MVT::i64) && "Unexpected return value type.");

43
test/CodeGen/AArch64/fast-isel-shift.ll
View File

@ -1,5 +1,48 @@
; RUN: llc -fast-isel -fast-isel-abort -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: lsr_zext_i1_i16
; CHECK: uxth {{w[0-9]*}}, wzr
define zeroext i16 @lsr_zext_i1_i16(i1 %b) {
%1 = zext i1 %b to i16
%2 = lshr i16 %1, 1
ret i16 %2
}
; CHECK-LABEL: lsr_sext_i1_i16
; CHECK: sbfx [[REG1:w[0-9]+]], {{w[0-9]*}}, #0, #1
; CHECK-NEXT: ubfx [[REG2:w[0-9]+]], [[REG1]], #1, #15
; CHECK-NEXT: sxth {{w[0-9]*}}, [[REG2]]
define signext i16 @lsr_sext_i1_i16(i1 %b) {
%1 = sext i1 %b to i16
%2 = lshr i16 %1, 1
ret i16 %2
}
; CHECK-LABEL: lsr_zext_i1_i32
; CHECK: mov {{w[0-9]*}}, wzr
define i32 @lsr_zext_i1_i32(i1 %b) {
%1 = zext i1 %b to i32
%2 = lshr i32 %1, 1
ret i32 %2
}
; CHECK-LABEL: lsr_sext_i1_i32
; CHECK: sbfx [[REG1:w[0-9]+]], {{w[0-9]*}}, #0, #1
; CHECK-NEXT: lsr {{w[0-9]*}}, [[REG1:w[0-9]+]], #1
define i32 @lsr_sext_i1_i32(i1 %b) {
%1 = sext i1 %b to i32
%2 = lshr i32 %1, 1
ret i32 %2
}
; CHECK-LABEL: lsr_zext_i1_i64
; CHECK: mov {{x[0-9]*}}, xzr
define i64 @lsr_zext_i1_i64(i1 %b) {
%1 = zext i1 %b to i64
%2 = lshr i64 %1, 1
ret i64 %2
}
; CHECK-LABEL: lsl_zext_i1_i16
; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
define zeroext i16 @lsl_zext_i1_i16(i1 %b) {