mirror of
https://github.com/c64scene-ar/llvm-6502.git
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NEON VLD3(all lanes) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
2527188a42
commit
5e59f7e15e
@ -171,6 +171,27 @@ def VecListTwoQAllLanes : RegisterOperand<DPR,
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"printVectorListTwoSpacedAllLanes"> {
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let ParserMatchClass = VecListTwoQAllLanesAsmOperand;
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}
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// Register list of three D registers, with "all lanes" subscripting.
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def VecListThreeDAllLanesAsmOperand : AsmOperandClass {
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let Name = "VecListThreeDAllLanes";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListOperands";
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}
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def VecListThreeDAllLanes : RegisterOperand<DPR,
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"printVectorListThreeAllLanes"> {
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let ParserMatchClass = VecListThreeDAllLanesAsmOperand;
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}
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// Register list of three D registers spaced by 2 (three sequential Q regs).
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def VecListThreeQAllLanesAsmOperand : AsmOperandClass {
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let Name = "VecListThreeQAllLanes";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListOperands";
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}
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def VecListThreeQAllLanes : RegisterOperand<DPR,
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"printVectorListThreeSpacedAllLanes"> {
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let ParserMatchClass = VecListThreeQAllLanesAsmOperand;
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}
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// Register list of one D register, with byte lane subscripting.
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def VecListOneDByteIndexAsmOperand : AsmOperandClass {
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@ -1433,9 +1454,9 @@ def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
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def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
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// ...with double-spaced registers (not used for codegen):
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def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
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def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
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def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
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def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
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def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
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def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
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// ...with address register writeback:
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class VLD3DUPWB<bits<4> op7_4, string Dt>
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@ -1451,9 +1472,9 @@ def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
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def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
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def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
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def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
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def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
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def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
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def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
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def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
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def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
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def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
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def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
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@ -6036,6 +6057,64 @@ def VST2LNqWB_register_Asm_32 :
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(ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VLD3 all-lanes pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
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(ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
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(ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
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(ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
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(ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
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(ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
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(ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPdWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
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(ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPdWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
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(ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPdWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
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(ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPqWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
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(ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPqWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
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(ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPqWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
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(ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPdWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
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(ins VecListThreeDAllLanes:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD3DUPdWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
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(ins VecListThreeDAllLanes:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD3DUPdWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
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(ins VecListThreeDAllLanes:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD3DUPqWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
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(ins VecListThreeQAllLanes:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD3DUPqWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
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(ins VecListThreeQAllLanes:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD3DUPqWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
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(ins VecListThreeQAllLanes:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VLD3 single-lane pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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@ -1132,6 +1132,16 @@ public:
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return VectorList.Count == 2;
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}
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bool isVecListThreeDAllLanes() const {
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if (!isSingleSpacedVectorAllLanes()) return false;
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return VectorList.Count == 3;
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}
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bool isVecListThreeQAllLanes() const {
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if (!isDoubleSpacedVectorAllLanes()) return false;
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return VectorList.Count == 3;
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}
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bool isSingleSpacedVectorIndexed() const {
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return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
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}
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@ -5343,6 +5353,26 @@ static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
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case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
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case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
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// VLD3DUP
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case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
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case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
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case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
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case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
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case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
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case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
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case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
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case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
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case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
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case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
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case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
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case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
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case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
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case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
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case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
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case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
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case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
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case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
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// VLD3LN
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case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
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case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
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@ -6061,6 +6091,77 @@ processInstruction(MCInst &Inst,
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return true;
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}
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// VLD3DUP single 3-element structure to all lanes instructions.
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case ARM::VLD3DUPdAsm_8:
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case ARM::VLD3DUPdAsm_16:
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case ARM::VLD3DUPdAsm_32:
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case ARM::VLD3DUPqAsm_8:
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case ARM::VLD3DUPqAsm_16:
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case ARM::VLD3DUPqAsm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(Inst.getOperand(3)); // CondCode
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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return true;
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}
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case ARM::VLD3DUPdWB_fixed_Asm_8:
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case ARM::VLD3DUPdWB_fixed_Asm_16:
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case ARM::VLD3DUPdWB_fixed_Asm_32:
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case ARM::VLD3DUPqWB_fixed_Asm_8:
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case ARM::VLD3DUPqWB_fixed_Asm_16:
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case ARM::VLD3DUPqWB_fixed_Asm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
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TmpInst.addOperand(Inst.getOperand(3)); // CondCode
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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return true;
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}
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case ARM::VLD3DUPdWB_register_Asm_8:
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case ARM::VLD3DUPdWB_register_Asm_16:
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case ARM::VLD3DUPdWB_register_Asm_32:
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case ARM::VLD3DUPqWB_register_Asm_8:
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case ARM::VLD3DUPqWB_register_Asm_16:
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case ARM::VLD3DUPqWB_register_Asm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(Inst.getOperand(3)); // Rm
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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Inst = TmpInst;
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return true;
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}
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// VLD3 multiple 3-element structure instructions.
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case ARM::VLD3dAsm_8:
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case ARM::VLD3dAsm_16:
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@ -1067,6 +1067,17 @@ void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[]}";
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}
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void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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// Normally, it's not safe to use register enum values directly with
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// addition to get the next register, but for VFP registers, the
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// sort order is guaranteed because they're all of the form D<n>.
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O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
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}
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void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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// Normally, it's not safe to use register enum values directly with
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@ -1086,6 +1097,17 @@ void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
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}
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void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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// Normally, it's not safe to use register enum values directly with
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// addition to get the next register, but for VFP registers, the
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// sort order is guaranteed because they're all of the form D<n>.
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O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
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}
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void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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@ -139,10 +139,14 @@ public:
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raw_ostream &O);
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void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
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@ -336,6 +336,47 @@
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@ CHECK: vld3.32 {d5[0], d7[0], d9[0]}, [r4]! @ encoding: [0x4d,0x5a,0xa4,0xf4]
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vld3.8 {d16[], d17[], d18[]}, [r1]
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vld3.16 {d16[], d17[], d18[]}, [r2]
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vld3.32 {d16[], d17[], d18[]}, [r3]
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vld3.8 {d17[], d19[], d21[]}, [r7]
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vld3.16 {d17[], d19[], d21[]}, [r7]
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vld3.32 {d16[], d18[], d20[]}, [r8]
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vld3.s8 {d16[], d17[], d18[]}, [r1]!
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vld3.s16 {d16[], d17[], d18[]}, [r2]!
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vld3.s32 {d16[], d17[], d18[]}, [r3]!
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vld3.u8 {d17[], d19[], d21[]}, [r7]!
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vld3.u16 {d17[], d19[], d21[]}, [r7]!
|
||||
vld3.u32 {d16[], d18[], d20[]}, [r8]!
|
||||
|
||||
vld3.p8 {d16[], d17[], d18[]}, [r1], r8
|
||||
vld3.p16 {d16[], d17[], d18[]}, [r2], r7
|
||||
vld3.f32 {d16[], d17[], d18[]}, [r3], r5
|
||||
vld3.i8 {d16[], d18[], d20[]}, [r6], r3
|
||||
vld3.i16 {d16[], d18[], d20[]}, [r6], r3
|
||||
vld3.i32 {d17[], d19[], d21[]}, [r9], r4
|
||||
|
||||
@ CHECK: vld3.8 {d16[], d17[], d18[]}, [r1] @ encoding: [0x0f,0x0e,0xe1,0xf4]
|
||||
@ CHECK: vld3.16 {d16[], d17[], d18[]}, [r2] @ encoding: [0x4f,0x0e,0xe2,0xf4]
|
||||
@ CHECK: vld3.32 {d16[], d17[], d18[]}, [r3] @ encoding: [0x8f,0x0e,0xe3,0xf4]
|
||||
@ CHECK: vld3.8 {d17[], d19[], d21[]}, [r7] @ encoding: [0x2f,0x1e,0xe7,0xf4]
|
||||
@ CHECK: vld3.16 {d17[], d19[], d21[]}, [r7] @ encoding: [0x6f,0x1e,0xe7,0xf4]
|
||||
@ CHECK: vld3.32 {d16[], d18[], d20[]}, [r8] @ encoding: [0xaf,0x0e,0xe8,0xf4]
|
||||
@ CHECK: vld3.8 {d16[], d17[], d18[]}, [r1]! @ encoding: [0x0d,0x0e,0xe1,0xf4]
|
||||
@ CHECK: vld3.16 {d16[], d17[], d18[]}, [r2]! @ encoding: [0x4d,0x0e,0xe2,0xf4]
|
||||
@ CHECK: vld3.32 {d16[], d17[], d18[]}, [r3]! @ encoding: [0x8d,0x0e,0xe3,0xf4]
|
||||
@ CHECK: vld3.8 {d17[], d18[], d19[]}, [r7]! @ encoding: [0x2d,0x1e,0xe7,0xf4]
|
||||
@ CHECK: vld3.16 {d17[], d18[], d19[]}, [r7]! @ encoding: [0x6d,0x1e,0xe7,0xf4]
|
||||
@ CHECK: vld3.32 {d16[], d18[], d20[]}, [r8]! @ encoding: [0xad,0x0e,0xe8,0xf4]
|
||||
@ CHECK: vld3.8 {d16[], d17[], d18[]}, [r1], r8 @ encoding: [0x08,0x0e,0xe1,0xf4]
|
||||
@ CHECK: vld3.16 {d16[], d17[], d18[]}, [r2], r7 @ encoding: [0x47,0x0e,0xe2,0xf4]
|
||||
@ CHECK: vld3.32 {d16[], d17[], d18[]}, [r3], r5 @ encoding: [0x85,0x0e,0xe3,0xf4]
|
||||
@ CHECK: vld3.8 {d16[], d18[], d20[]}, [r6], r3 @ encoding: [0x23,0x0e,0xe6,0xf4]
|
||||
@ CHECK: vld3.16 {d16[], d18[], d20[]}, [r6], r3 @ encoding: [0x63,0x0e,0xe6,0xf4]
|
||||
@ CHECK: vld3.32 {d17[], d19[], d21[]}, [r9], r4 @ encoding: [0xa4,0x1e,0xe9,0xf4]
|
||||
|
||||
|
||||
vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1]
|
||||
vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2]
|
||||
vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3]
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user