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misched: Added ScheduleDAGInstrs::IsPostRA

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148172 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-01-14 02:17:12 +00:00
parent e9ef4ed13b
commit 5e920d7c83
4 changed files with 17 additions and 11 deletions
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4
lib/CodeGen/MachineScheduler.cpp
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@ -157,7 +157,7 @@ class MachineScheduler : public ScheduleDAGInstrs {
MachineSchedulerPass *Pass;
public:
MachineScheduler(MachineSchedulerPass *P):
ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT), Pass(P) {}
ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
/// time to do some work.
@ -252,7 +252,7 @@ class InstructionShuffler : public ScheduleDAGInstrs {
MachineSchedulerPass *Pass;
public:
InstructionShuffler(MachineSchedulerPass *P):
ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT), Pass(P) {}
ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
/// time to do some work.

2
lib/CodeGen/PostRASchedulerList.cpp
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@ -185,7 +185,7 @@ SchedulePostRATDList::SchedulePostRATDList(
AliasAnalysis *AA, const RegisterClassInfo &RCI,
TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
SmallVectorImpl<TargetRegisterClass*> &CriticalPathRCs)
: ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits), AA(AA),
: ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), Topo(SUnits), AA(AA),
KillIndices(TRI->getNumRegs())
{
const TargetMachine &TM = MF.getTarget();

8
lib/CodeGen/ScheduleDAGInstrs.cpp
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@ -33,9 +33,10 @@ using namespace llvm;
ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo &mli,
const MachineDominatorTree &mdt)
const MachineDominatorTree &mdt,
bool IsPostRAFlag)
: ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
InstrItins(mf.getTarget().getInstrItineraryData()),
InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag),
Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()),
LoopRegs(MLI, MDT), FirstDbgValue(0) {
DbgValues.clear();
@ -253,7 +254,8 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
assert(!IsPostRA || TRI->isPhysicalRegister(Reg) &&
"Virtual register encountered!");
// Optionally add output and anti dependencies. For anti
// dependencies we use a latency of 0 because for a multi-issue

14
lib/CodeGen/ScheduleDAGInstrs.h
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@ -104,10 +104,13 @@ namespace llvm {
const MachineFrameInfo *MFI;
const InstrItineraryData *InstrItins;
/// Defs, Uses - Remember where defs and uses of each physical register
/// are as we iterate upward through the instructions. This is allocated
/// here instead of inside BuildSchedGraph to avoid the need for it to be
/// initialized and destructed for each block.
/// isPostRA flag indicates vregs cannot be present.
bool IsPostRA;
/// Defs, Uses - Remember where defs and uses of each register are as we
/// iterate upward through the instructions. This is allocated here instead
/// of inside BuildSchedGraph to avoid the need for it to be initialized and
/// destructed for each block.
std::vector<std::vector<SUnit *> > Defs;
std::vector<std::vector<SUnit *> > Uses;
@ -136,7 +139,8 @@ namespace llvm {
explicit ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo &mli,
const MachineDominatorTree &mdt);
const MachineDominatorTree &mdt,
bool IsPostRAFlag);
virtual ~ScheduleDAGInstrs() {}