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Changed my mind. We now allow remat of instructions whose defs have subreg indices.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76100 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-07-16 20:15:00 +00:00
parent 914e50c841
commit 5f15992b77
3 changed files with 9 additions and 10 deletions
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5
lib/CodeGen/LiveIntervalAnalysis.cpp
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@ -1157,11 +1157,6 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
if (DisableReMat)
return false;
// FIXME: For now, avoid remating instructions whose definition has a subreg
// index. It's just incredibly difficult to get right.
if (MI->findRegisterDefOperand(li.reg)->getSubReg())
return false;
if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
return true;

9
lib/CodeGen/VirtRegRewriter.cpp
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@ -490,7 +490,14 @@ static void ReMaterialize(MachineBasicBlock &MBB,
const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI,
VirtRegMap &VRM) {
TII->reMaterialize(MBB, MII, DestReg, 0, VRM.getReMaterializedMI(Reg));
MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg);
#ifdef NDEBUG
const TargetInstrDesc &TID = ReMatDefMI->getDesc();
assert(TID.getNumDefs() != 1 &&
"Don't know how to remat instructions that define > 1 values!");
#endif
TII->reMaterialize(MBB, MII, DestReg,
ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI);
MachineInstr *NewMI = prior(MII);
for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = NewMI->getOperand(i);

5
test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
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@ -1,10 +1,7 @@
; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movd | count 1
; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movq
; PR2677
; FIXME: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movd | count 1
; We now no longer allow instruction whose def has a sub-reg index to be
; rematerialized.
%struct.Bigint = type { %struct.Bigint*, i32, i32, i32, i32, [1 x i32] }