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Switch AllocationOrder to using RegisterClassInfo instead of a BitVector

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of reserved registers.

Use RegisterClassInfo in RABasic as well. This slightly changes som
allocation orders because RegisterClassInfo puts CSR aliases last.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132581 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-06-03 20:34:53 +00:00
parent d365fa9415
commit 5f2316a3b5
6 changed files with 19 additions and 23 deletions
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9
lib/CodeGen/AllocationOrder.cpp
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@ -15,6 +15,7 @@
//===----------------------------------------------------------------------===//
#include "AllocationOrder.h"
#include "RegisterClassInfo.h"
#include "VirtRegMap.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@ -23,8 +24,8 @@ using namespace llvm;
// Compare VirtRegMap::getRegAllocPref().
AllocationOrder::AllocationOrder(unsigned VirtReg,
const VirtRegMap &VRM,
const BitVector &ReservedRegs)
: Pos(0), Reserved(ReservedRegs) {
const RegisterClassInfo &RegClassInfo)
: Pos(0), RCI(RegClassInfo) {
const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
std::pair<unsigned, unsigned> HintPair =
VRM.getRegInfo().getRegAllocationHint(VirtReg);
@ -47,7 +48,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
// The hint must be a valid physreg for allocation.
if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
!RC->contains(Hint) || ReservedRegs.test(Hint)))
!RC->contains(Hint) || RCI.isReserved(Hint)))
Hint = 0;
}
@ -61,7 +62,7 @@ unsigned AllocationOrder::next() {
// Then look at the order from TRI.
while(Pos != End) {
unsigned Reg = *Pos++;
if (Reg != Hint && !Reserved.test(Reg))
if (Reg != Hint && !RCI.isReserved(Reg))
return Reg;
}
return 0;