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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 07:11:49 +00:00
R600: Add dag combine for copy of an illegal type.
This helps avoid redundant instructions to unpack, and repack the vectors. Ideally we could recognize that pattern and eliminate it. Currently v4i8 and other small element type vectors are scalarized, so this has the added bonus of avoiding that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213031 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
832e3ffdb0
commit
5fbf09a69f
@ -360,6 +360,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setTargetDAGCombine(ISD::MUL);
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::STORE);
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setSchedulingPreference(Sched::RegPressure);
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setJumpIsExpensive(true);
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@ -1896,6 +1897,56 @@ static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
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return DAG.getConstant(Src0 >> Offset, MVT::i32);
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}
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static bool usesAllNormalStores(SDNode *LoadVal) {
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for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
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if (!ISD::isNormalStore(*I))
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return false;
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}
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return true;
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}
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// If we have a copy of an illegal type, replace it with a load / store of an
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// equivalently sized legal type. This avoids intermediate bit pack / unpack
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// instructions emitted when handling extloads and truncstores. Ideally we could
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// recognize the pack / unpack pattern to eliminate it.
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SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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if (!DCI.isBeforeLegalize())
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return SDValue();
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StoreSDNode *SN = cast<StoreSDNode>(N);
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SDValue Value = SN->getValue();
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EVT VT = Value.getValueType();
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if (isTypeLegal(VT) || SN->isVolatile() || !ISD::isNormalLoad(Value.getNode()))
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return SDValue();
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LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
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if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
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return SDValue();
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EVT MemVT = LoadVal->getMemoryVT();
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SDLoc SL(N);
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SelectionDAG &DAG = DCI.DAG;
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EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
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SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
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LoadVT, SL,
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LoadVal->getChain(),
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LoadVal->getBasePtr(),
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LoadVal->getOffset(),
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LoadVT,
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LoadVal->getMemOperand());
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SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
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DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
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return DAG.getStore(SN->getChain(), SL, NewLoad,
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SN->getBasePtr(), SN->getMemOperand());
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}
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SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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EVT VT = N->getValueType(0);
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@ -1928,7 +1979,7 @@ SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
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}
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SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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SDLoc DL(N);
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@ -2026,6 +2077,9 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
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break;
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}
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case ISD::STORE:
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return performStoreCombine(N, DCI);
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}
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return SDValue();
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}
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@ -64,6 +64,7 @@ private:
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SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
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SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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protected:
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166
test/CodeGen/R600/copy-illegal-type.ll
Normal file
166
test/CodeGen/R600/copy-illegal-type.ll
Normal file
@ -0,0 +1,166 @@
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; RUN: llc -march=r600 -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FUNC-LABEL: @test_copy_v4i8
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; SI: BUFFER_LOAD_DWORD [[REG:v[0-9]+]]
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; SI: BUFFER_STORE_DWORD [[REG]]
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; SI: S_ENDPGM
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define void @test_copy_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
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%val = load <4 x i8> addrspace(1)* %in, align 4
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @test_copy_v4i8_x2
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; SI: BUFFER_LOAD_DWORD [[REG:v[0-9]+]]
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; SI: BUFFER_STORE_DWORD [[REG]]
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; SI: BUFFER_STORE_DWORD [[REG]]
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; SI: S_ENDPGM
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define void @test_copy_v4i8_x2(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind {
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%val = load <4 x i8> addrspace(1)* %in, align 4
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4
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ret void
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}
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; FUNC-LABEL: @test_copy_v4i8_x3
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; SI: BUFFER_LOAD_DWORD [[REG:v[0-9]+]]
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; SI: BUFFER_STORE_DWORD [[REG]]
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; SI: BUFFER_STORE_DWORD [[REG]]
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; SI: BUFFER_STORE_DWORD [[REG]]
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; SI: S_ENDPGM
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define void @test_copy_v4i8_x3(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind {
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%val = load <4 x i8> addrspace(1)* %in, align 4
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4
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ret void
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}
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; FUNC-LABEL: @test_copy_v4i8_x4
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; SI: BUFFER_LOAD_DWORD [[REG:v[0-9]+]]
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; SI: BUFFER_STORE_DWORD [[REG]]
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; SI: BUFFER_STORE_DWORD [[REG]]
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; SI: BUFFER_STORE_DWORD [[REG]]
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; SI: BUFFER_STORE_DWORD [[REG]]
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; SI: S_ENDPGM
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define void @test_copy_v4i8_x4(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %out3, <4 x i8> addrspace(1)* %in) nounwind {
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%val = load <4 x i8> addrspace(1)* %in, align 4
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out3, align 4
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ret void
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}
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; FUNC-LABEL: @test_copy_v4i8_extra_use
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_LOAD_UBYTE
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; SI-DAG: V_ADD
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; SI-DAG: V_ADD
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; SI-DAG: V_ADD
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; SI-DAG: V_ADD
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI_DAG: BUFFER_STORE_BYTE
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; After scalarizing v4i8 loads is fixed.
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; XSI: BUFFER_LOAD_DWORD
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; XSI: V_BFE
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; XSI: V_ADD
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; XSI: V_ADD
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; XSI: V_ADD
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; XSI: BUFFER_STORE_DWORD
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; XSI: BUFFER_STORE_DWORD
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; SI: S_ENDPGM
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define void @test_copy_v4i8_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind {
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%val = load <4 x i8> addrspace(1)* %in, align 4
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%add = add <4 x i8> %val, <i8 9, i8 9, i8 9, i8 9>
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
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store <4 x i8> %add, <4 x i8> addrspace(1)* %out1, align 4
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ret void
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}
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; FUNC-LABEL: @test_copy_v4i8_x2_extra_use
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_LOAD_UBYTE
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; SI-DAG: V_ADD
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; SI-DAG: V_ADD
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; SI-DAG: V_ADD
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; SI-DAG: V_ADD
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI_DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI-DAG: BUFFER_STORE_BYTE
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; SI_DAG: BUFFER_STORE_BYTE
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; XSI: BUFFER_LOAD_DWORD
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; XSI: BFE
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; XSI: BUFFER_STORE_DWORD
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; XSI: V_ADD
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; XSI: BUFFER_STORE_DWORD
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; XSI-NEXT: BUFFER_STORE_DWORD
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; SI: S_ENDPGM
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define void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind {
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%val = load <4 x i8> addrspace(1)* %in, align 4
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%add = add <4 x i8> %val, <i8 9, i8 9, i8 9, i8 9>
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
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store <4 x i8> %add, <4 x i8> addrspace(1)* %out1, align 4
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4
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ret void
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}
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; FUNC-LABEL: @test_copy_v3i8
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; SI-NOT: BFE
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; SI-NOT: BFI
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; SI: S_ENDPGM
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define void @test_copy_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) nounwind {
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%val = load <3 x i8> addrspace(1)* %in, align 4
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store <3 x i8> %val, <3 x i8> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @test_copy_v4i8_volatile_load
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_LOAD_UBYTE
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; SI: S_ENDPGM
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define void @test_copy_v4i8_volatile_load(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
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%val = load volatile <4 x i8> addrspace(1)* %in, align 4
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store <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @test_copy_v4i8_volatile_store
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_STORE_BYTE
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; SI: BUFFER_STORE_BYTE
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; SI: BUFFER_STORE_BYTE
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; SI: BUFFER_STORE_BYTE
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; SI: S_ENDPGM
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define void @test_copy_v4i8_volatile_store(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
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%val = load <4 x i8> addrspace(1)* %in, align 4
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store volatile <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
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ret void
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}
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@ -31,10 +31,14 @@ define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double
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; SI-ALLOCA: V_MOVRELS_B32_e32
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; SI-ALLOCA: V_MOVRELS_B32_e32
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; SI-PROMOTE: DS_WRITE_B64
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; SI-PROMOTE: DS_WRITE_B64
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; SI-PROMOTE: DS_READ_B64
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; SI-PROMOTE: DS_READ_B64
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; SI-PROMOTE: DS_WRITE_B32
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; SI-PROMOTE: DS_WRITE_B32
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; SI-PROMOTE: DS_WRITE_B32
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; SI-PROMOTE: DS_WRITE_B32
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; SI-PROMOTE: DS_READ_B32
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; SI-PROMOTE: DS_READ_B32
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; SI-PROMOTE: DS_READ_B32
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; SI-PROMOTE: DS_READ_B32
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define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) nounwind {
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%val = load <2 x double> addrspace(1)* %in, align 16
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%array = alloca <2 x double>, i32 16, align 16
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@ -77,10 +81,14 @@ define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrs
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; SI-ALLOCA: V_MOVRELS_B32_e32
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; SI-ALLOCA: V_MOVRELS_B32_e32
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; SI-PROMOTE: DS_WRITE_B64
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; SI-PROMOTE: DS_WRITE_B64
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; SI-PROMOTE: DS_READ_B64
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; SI-PROMOTE: DS_READ_B64
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; SI-PROMOTE: DS_WRITE_B32
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; SI-PROMOTE: DS_WRITE_B32
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; SI-PROMOTE: DS_WRITE_B32
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; SI-PROMOTE: DS_WRITE_B32
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; SI-PROMOTE: DS_READ_B32
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; SI-PROMOTE: DS_READ_B32
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; SI-PROMOTE: DS_READ_B32
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; SI-PROMOTE: DS_READ_B32
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define void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) nounwind {
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%val = load <2 x i64> addrspace(1)* %in, align 16
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%array = alloca <2 x i64>, i32 16, align 16
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@ -254,8 +254,8 @@ entry:
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; load a v2f32 value from the global address space
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; FUNC-LABEL: @load_v2f32
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; R600-CHECK: MEM_RAT
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; R600-CHECK: VTX_READ_64
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; SI-CHECK: BUFFER_LOAD_DWORDX2
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define void @load_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) {
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entry:
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@ -265,9 +265,7 @@ entry:
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}
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; FUNC-LABEL: @load_i64
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; R600-CHECK: MEM_RAT
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; R600-CHECK: MEM_RAT
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; R600-CHECK: VTX_READ_64
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; SI-CHECK: BUFFER_LOAD_DWORDX2
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define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
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entry:
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