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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104111 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
3c3195cbf1
commit
5fd1c9be2d
@ -1141,7 +1141,8 @@ def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
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[(set GPR:$dst, (load addrmode2:$addr))]>;
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// Special LDR for loads from non-pc-relative constpools.
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let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
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let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
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isReMaterializable = 1 in
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def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
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"ldr", "\t$dst, $addr", []>;
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@ -1163,7 +1164,7 @@ def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
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IIC_iLoadr, "ldrsb", "\t$dst, $addr",
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[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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// Load doubleword
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def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
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IIC_iLoadr, "ldrd", "\t$dst1, $addr",
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@ -1222,7 +1223,7 @@ def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
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"ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
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Requires<[IsARM, HasV5TE]>;
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}
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} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
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// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
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@ -1271,7 +1272,7 @@ def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
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[(truncstorei8 GPR:$src, addrmode2:$addr)]>;
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// Store doubleword
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
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def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
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StMiscFrm, IIC_iStorer,
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"strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
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@ -1363,7 +1364,7 @@ def STRHT: AI3sthpo<(outs GPR:$base_wb),
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// Load / store multiple Instructions.
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//
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
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reglist:$dsts, variable_ops),
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IndexModeNone, LdStMulFrm, IIC_iLoadm,
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@ -1374,9 +1375,9 @@ def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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IndexModeUpd, LdStMulFrm, IIC_iLoadm,
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"ldm${addr:submode}${p}\t$addr!, $dsts",
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"$addr.addr = $wb", []>;
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} // mayLoad, hasExtraDefRegAllocReq
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} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p,
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reglist:$srcs, variable_ops),
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IndexModeNone, LdStMulFrm, IIC_iStorem,
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@ -1387,7 +1388,7 @@ def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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IndexModeUpd, LdStMulFrm, IIC_iStorem,
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"stm${addr:submode}${p}\t$addr!, $srcs",
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"$addr.addr = $wb", []>;
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} // mayStore, hasExtraSrcRegAllocReq
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} // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
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//===----------------------------------------------------------------------===//
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// Move Instructions.
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@ -115,7 +115,7 @@ def h64imm : Operand<i64> {
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// NEON load / store instructions
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//===----------------------------------------------------------------------===//
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let mayLoad = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1 in {
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// Use vldmia to load a Q register as a D register pair.
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// This is equivalent to VLDMD except that it has a Q register operand
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// instead of a pair of D registers.
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@ -130,9 +130,9 @@ def VLDMQ
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def VLD1q
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: NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst), (ins addrmode6:$addr),
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IIC_VLD1, "vld1", "64", "${dst:dregpair}, $addr", "", []>;
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} // mayLoad = 1
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} // mayLoad = 1, neverHasSideEffects = 1
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let mayStore = 1 in {
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let mayStore = 1, neverHasSideEffects = 1 in {
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// Use vstmia to store a Q register as a D register pair.
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// This is equivalent to VSTMD except that it has a Q register operand
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// instead of a pair of D registers.
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@ -147,9 +147,9 @@ def VSTMQ
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def VST1q
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: NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, QPR:$src),
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IIC_VST, "vst1", "64", "${src:dregpair}, $addr", "", []>;
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} // mayStore = 1
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} // mayStore = 1, neverHasSideEffects = 1
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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// VLD1 : Vector Load (multiple single elements)
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class VLD1D<bits<4> op7_4, string Dt>
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@ -473,9 +473,9 @@ def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
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// VLD3DUP : Vector Load (single 3-element structure to all lanes)
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// VLD4DUP : Vector Load (single 4-element structure to all lanes)
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// FIXME: Not yet implemented.
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} // mayLoad = 1, hasExtraDefRegAllocReq = 1
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} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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// VST1 : Vector Store (multiple single elements)
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class VST1D<bits<4> op7_4, string Dt>
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@ -788,7 +788,7 @@ def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">;
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def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">;
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def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">;
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} // mayStore = 1, hasExtraSrcRegAllocReq = 1
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} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
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//===----------------------------------------------------------------------===//
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@ -480,7 +480,7 @@ def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
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// Special instruction for restore. It cannot clobber condition register
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// when it's expanded by eliminateCallFramePseudoInstr().
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let canFoldAsLoad = 1, mayLoad = 1 in
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let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
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def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
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"ldr", "\t$dst, $addr", []>,
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T1LdStSP<{1,?,?}>;
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@ -494,7 +494,8 @@ def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
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T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
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// Special LDR for loads from non-pc-relative constpools.
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let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
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let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
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isReMaterializable = 1 in
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def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
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"ldr", "\t$dst, $addr", []>,
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T1LdStSP<{1,?,?}>;
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@ -531,7 +532,7 @@ def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
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[(store tGPR:$src, t_addrmode_sp:$addr)]>,
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T1LdStSP<{0,?,?}>;
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let mayStore = 1 in {
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let mayStore = 1, neverHasSideEffects = 1 in {
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// Special instruction for spill. It cannot clobber condition register
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// when it's expanded by eliminateCallFramePseudoInstr().
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def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
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@ -544,7 +545,7 @@ def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
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//
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// These requires base address to be written back or one of the loaded regs.
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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def tLDM : T1I<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops),
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IIC_iLoadm,
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@ -557,9 +558,9 @@ def tLDM_UPD : T1It<(outs tGPR:$wb),
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"ldm${addr:submode}${p}\t$addr!, $dsts",
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"$addr.addr = $wb", []>,
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T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
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} // mayLoad, hasExtraDefRegAllocReq
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} // mayLoad, neverHasSideEffects = 1, hasExtraDefRegAllocReq
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
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def tSTM_UPD : T1It<(outs tGPR:$wb),
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(ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops),
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IIC_iStorem,
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@ -914,7 +914,7 @@ defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
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defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
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defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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// Load doubleword
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def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
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(ins t2addrmode_imm8s4:$addr),
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@ -924,7 +924,7 @@ def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
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"ldrd", "\t$dst1, $addr", []> {
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let Inst{19-16} = 0b1111; // Rn
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}
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}
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} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
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// zextload i1 -> zextload i8
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def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
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@ -967,7 +967,7 @@ def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
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(t2LDRHpci tconstpool:$addr)>;
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// Indexed loads
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let mayLoad = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1 in {
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def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
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(ins t2addrmode_imm8:$addr),
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AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
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@ -1023,7 +1023,7 @@ def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
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AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
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"ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
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[]>;
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}
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} // mayLoad = 1, neverHasSideEffects = 1
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// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
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// for disassembly only.
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@ -1053,7 +1053,7 @@ defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
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defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
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// Store doubleword
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let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
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def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
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(ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
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IIC_iStorer, "strd", "\t$src1, $addr", []>;
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@ -1216,7 +1216,7 @@ defm t2PLI : T2Ipl<1, 0, "pli">;
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// Load / store multiple Instructions.
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//
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
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reglist:$dsts, variable_ops), IIC_iLoadm,
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"ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> {
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@ -1239,9 +1239,9 @@ def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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let Inst{21} = 1; // The W bit.
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let Inst{20} = 1; // Load
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}
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} // mayLoad, hasExtraDefRegAllocReq
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} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
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reglist:$srcs, variable_ops), IIC_iStorem,
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"stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> {
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@ -1265,7 +1265,7 @@ def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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let Inst{21} = 1; // The W bit.
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let Inst{20} = 0; // Store
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}
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} // mayStore, hasExtraSrcRegAllocReq
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} // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
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//===----------------------------------------------------------------------===//
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// Move Instructions.
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@ -76,7 +76,7 @@ def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
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// Load / store multiple Instructions.
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//
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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def VLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dsts,
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variable_ops), IndexModeNone, IIC_fpLoadm,
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"vldm${addr:submode}${p}\t${addr:base}, $dsts", "", []> {
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@ -104,9 +104,9 @@ def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
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"$addr.base = $wb", []> {
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let Inst{20} = 1;
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}
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} // mayLoad, hasExtraDefRegAllocReq
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} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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def VSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$srcs,
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variable_ops), IndexModeNone, IIC_fpStorem,
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"vstm${addr:submode}${p}\t${addr:base}, $srcs", "", []> {
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@ -134,7 +134,7 @@ def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
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"$addr.base = $wb", []> {
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let Inst{20} = 0;
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}
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} // mayStore, hasExtraSrcRegAllocReq
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} // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
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// FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
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