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Enable allocation of R3 in Thumb1

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2009-10-19 22:57:03 +00:00
parent 5a207897bc
commit 6009751244
5 changed files with 4 additions and 18 deletions
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6
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -740,8 +740,7 @@ unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
case ARM::R1:
return ARM::R0;
case ARM::R3:
// FIXME!
return STI.isThumb1Only() ? 0 : ARM::R2;
return ARM::R2;
case ARM::R5:
return ARM::R4;
case ARM::R7:
@ -830,8 +829,7 @@ unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
case ARM::R0:
return ARM::R1;
case ARM::R2:
// FIXME!
return STI.isThumb1Only() ? 0 : ARM::R3;
return ARM::R3;
case ARM::R4:
return ARM::R5;
case ARM::R6:

5
lib/Target/ARM/ARMRegisterInfo.td
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@ -222,12 +222,9 @@ def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
}];
// FIXME: We are reserving r3 in Thumb mode in case the PEI needs to use it
// to generate large stack offset. Make it available once we have register
// scavenging.
let MethodBodies = [{
static const unsigned THUMB_tGPR_AO[] = {
ARM::R0, ARM::R1, ARM::R2,
ARM::R0, ARM::R1, ARM::R2, ARM::R3,
ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
// FP is R7, only low registers available.

8
lib/Target/ARM/README-Thumb.txt
View File

@ -196,14 +196,6 @@ This is especially bad when dynamic alloca is used. The all fixed size stack
objects are referenced off the frame pointer with negative offsets. See
oggenc for an example.
//===---------------------------------------------------------------------===//
We are reserving R3 as a scratch register under thumb mode. So if it is live in
to the function, we save / restore R3 to / from R12. Until register scavenging
is done, we should save R3 to a high callee saved reg at emitPrologue time
(when hasFP is true or stack size is large) and restore R3 from that register
instead. This allows us to at least get rid of the save to r12 everytime it is
used.
//===---------------------------------------------------------------------===//

1
lib/Target/ARM/Thumb1RegisterInfo.cpp
View File

@ -845,7 +845,6 @@ void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
if (VARegSaveSize) {
// Epilogue for vararg functions: pop LR to R3 and branch off it.
// FIXME: Verify this is still ok when R3 is no longer being reserved.
AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
.addReg(0) // No write back.
.addReg(ARM::R3, RegState::Define);

2
test/CodeGen/Thumb/2009-08-20-ISelBug.ll
View File

@ -11,7 +11,7 @@
define arm_apcscc i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize {
; CHECK: t:
; CHECK: adds r4, #8
; CHECK: adds r3, #8
entry:
%val = alloca i64, align 4 ; <i64*> [#uses=3]
%0 = icmp eq %struct.asl_file_t* %s, null ; <i1> [#uses=1]