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Enable two-address remat by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52701 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -53,10 +53,6 @@ STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
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STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
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STATISTIC(NumReMats, "Number of instructions re-materialized");
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static cl::opt<bool>
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EnableReMat("two-addr-remat", cl::init(false), cl::Hidden,
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cl::desc("Two-addr conversion should remat when possible."));
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namespace {
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class VISIBILITY_HIDDEN TwoAddressInstructionPass
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: public MachineFunctionPass {
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@ -71,8 +67,8 @@ namespace {
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bool isSafeToReMat(unsigned DstReg, MachineInstr *MI);
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bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
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MachineInstr *MI, unsigned Loc,
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MachineInstr *DefMI, MachineBasicBlock *MBB,
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MachineInstr *MI, MachineInstr *DefMI,
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MachineBasicBlock *MBB, unsigned Loc,
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DenseMap<MachineInstr*, unsigned> &DistanceMap);
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public:
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static char ID; // Pass identification, replacement for typeid
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@ -248,12 +244,9 @@ static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
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bool
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TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
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const TargetRegisterClass *RC,
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MachineInstr *MI, unsigned Loc,
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MachineInstr *DefMI, MachineBasicBlock *MBB,
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DenseMap<MachineInstr*, unsigned> &DistanceMap) {
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if (DefMI->getParent() != MBB)
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return true;
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// If earlier uses in MBB are not two-address uses, then don't remat.
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MachineInstr *MI, MachineInstr *DefMI,
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MachineBasicBlock *MBB, unsigned Loc,
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DenseMap<MachineInstr*, unsigned> &DistanceMap){
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bool OtherUse = false;
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for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
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UE = MRI->use_end(); UI != UE; ++UI) {
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@ -261,18 +254,26 @@ TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
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if (!UseMO.isUse())
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continue;
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MachineInstr *UseMI = UseMO.getParent();
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if (UseMI->getParent() != MBB)
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continue;
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DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
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if (DI != DistanceMap.end() && DI->second == Loc)
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continue; // Current use.
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OtherUse = true;
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// There is at least one other use in the MBB that will clobber the
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// register.
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if (isTwoAddrUse(UseMI, Reg))
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return true;
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (UseMBB == MBB) {
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DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
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if (DI != DistanceMap.end() && DI->second == Loc)
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continue; // Current use.
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OtherUse = true;
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// There is at least one other use in the MBB that will clobber the
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// register.
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if (isTwoAddrUse(UseMI, Reg))
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return true;
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}
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}
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return !OtherUse;
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// If other uses in MBB are not two-address uses, then don't remat.
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if (OtherUse)
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return false;
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// No other uses in the same block, remat if it's defined in the same
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// block so it does not unnecessarily extend the live range.
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return MBB == DefMI->getParent();
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}
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/// runOnMachineFunction - Reduce two-address instructions to two operands.
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@ -428,9 +429,9 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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MachineInstr *DefMI = MRI->getVRegDef(regB);
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// If it's safe and profitable, remat the definition instead of
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// copying it.
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if (EnableReMat && DefMI &&
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if (DefMI &&
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isSafeToReMat(regB, DefMI) &&
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isProfitableToReMat(regB, rc, mi, Dist, DefMI, mbbi,DistanceMap)){
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isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist,DistanceMap)){
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DEBUG(cerr << "2addr: REMATTING : " << *DefMI << "\n");
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TII->reMaterialize(*mbbi, mi, regA, DefMI);
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ReMatRegs.set(regB);
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@ -473,17 +474,14 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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}
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}
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if (EnableReMat) {
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// Some remat'ed instructions are dead.
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int VReg = ReMatRegs.find_first();
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while (VReg != -1) {
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if (MRI->use_empty(VReg)) {
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MachineInstr *DefMI = MRI->getVRegDef(VReg);
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DefMI->eraseFromParent();
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}
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VReg = ReMatRegs.find_next(VReg);
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// Some remat'ed instructions are dead.
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int VReg = ReMatRegs.find_first();
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while (VReg != -1) {
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if (MRI->use_empty(VReg)) {
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MachineInstr *DefMI = MRI->getVRegDef(VReg);
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DefMI->eraseFromParent();
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}
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VReg = ReMatRegs.find_next(VReg);
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}
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return MadeChange;
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@ -199,7 +199,7 @@ let neverHasSideEffects = 1 in
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def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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let isReMaterializable = 1 in {
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
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"movabs{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, imm:$src)]>;
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@ -3,7 +3,7 @@
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declare fastcc void @rdft(i32, i32, double*, i32*, double*)
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define fastcc void @mp_sqrt(i32 %n, i32 %radix, i32* %in, i32* %out, i32* %tmp1, i32* %tmp2, i32 %nfft, double* %tmp1fft, double* %tmp2fft, i32* %ip, double* %w) {
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define fastcc void @mp_sqrt(i32 %n, i32 %radix, i32* %in, i32* %out, i32* %tmp1, i32* %tmp2, i32 %nfft, double* %tmp1fft, double* %tmp2fft, i32* %ip, double* %w) nounwind {
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entry:
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br label %bb.i5
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67
test/CodeGen/X86/twoaddr-remat.ll
Normal file
67
test/CodeGen/X86/twoaddr-remat.ll
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@ -0,0 +1,67 @@
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; RUN: llvm-as < %s | llc -march=x86 | grep 59796 | count 3
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%Args = type %Value*
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%Exec = type opaque*
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%Identifier = type opaque*
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%JSFunction = type %Value (%Exec, %Scope, %Value, %Args)
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%PropertyNameArray = type opaque*
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%Scope = type opaque*
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%Value = type opaque*
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declare i1 @X1(%Exec) readonly
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declare %Value @X2(%Exec)
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declare i32 @X3(%Exec, %Value)
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declare %Value @X4(i32) readnone
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define internal %Value @fast3bitlookup(%Exec %exec, %Scope %scope, %Value %this, %Args %args) nounwind {
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prologue:
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%eh_check = tail call i1 @X1( %Exec %exec ) readonly ; <i1> [#uses=1]
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br i1 %eh_check, label %exception, label %no_exception
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exception: ; preds = %no_exception, %prologue
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%rethrow_result = tail call %Value @X2( %Exec %exec ) ; <%Value> [#uses=1]
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ret %Value %rethrow_result
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no_exception: ; preds = %prologue
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%args_intptr = bitcast %Args %args to i32* ; <i32*> [#uses=1]
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%argc_val = load i32* %args_intptr ; <i32> [#uses=1]
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%cmpParamArgc = icmp sgt i32 %argc_val, 0 ; <i1> [#uses=1]
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%arg_ptr = getelementptr %Args %args, i32 1 ; <%Args> [#uses=1]
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%arg_val = load %Args %arg_ptr ; <%Value> [#uses=1]
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%ext_arg_val = select i1 %cmpParamArgc, %Value %arg_val, %Value inttoptr (i32 5 to %Value) ; <%Value> [#uses=1]
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%toInt325 = tail call i32 @X3( %Exec %exec, %Value %ext_arg_val ) ; <i32> [#uses=3]
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%eh_check6 = tail call i1 @X1( %Exec %exec ) readonly ; <i1> [#uses=1]
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br i1 %eh_check6, label %exception, label %no_exception7
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no_exception7: ; preds = %no_exception
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%shl_tmp_result = shl i32 %toInt325, 1 ; <i32> [#uses=1]
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%rhs_masked13 = and i32 %shl_tmp_result, 14 ; <i32> [#uses=1]
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%ashr_tmp_result = lshr i32 59796, %rhs_masked13 ; <i32> [#uses=1]
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%and_tmp_result15 = and i32 %ashr_tmp_result, 3 ; <i32> [#uses=1]
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%ashr_tmp_result3283 = lshr i32 %toInt325, 2 ; <i32> [#uses=1]
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%rhs_masked38 = and i32 %ashr_tmp_result3283, 14 ; <i32> [#uses=1]
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%ashr_tmp_result39 = lshr i32 59796, %rhs_masked38 ; <i32> [#uses=1]
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%and_tmp_result41 = and i32 %ashr_tmp_result39, 3 ; <i32> [#uses=1]
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%addconv = add i32 %and_tmp_result15, %and_tmp_result41 ; <i32> [#uses=1]
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%ashr_tmp_result6181 = lshr i32 %toInt325, 5 ; <i32> [#uses=1]
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%rhs_masked67 = and i32 %ashr_tmp_result6181, 6 ; <i32> [#uses=1]
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%ashr_tmp_result68 = lshr i32 59796, %rhs_masked67 ; <i32> [#uses=1]
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%and_tmp_result70 = and i32 %ashr_tmp_result68, 3 ; <i32> [#uses=1]
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%addconv82 = add i32 %addconv, %and_tmp_result70 ; <i32> [#uses=3]
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%rangetmp = add i32 %addconv82, 536870912 ; <i32> [#uses=1]
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%rangecmp = icmp ult i32 %rangetmp, 1073741824 ; <i1> [#uses=1]
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br i1 %rangecmp, label %NumberLiteralIntFast, label %NumberLiteralIntSlow
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NumberLiteralIntFast: ; preds = %no_exception7
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%imm_shift = shl i32 %addconv82, 2 ; <i32> [#uses=1]
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%imm_or = or i32 %imm_shift, 3 ; <i32> [#uses=1]
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%imm_val = inttoptr i32 %imm_or to %Value ; <%Value> [#uses=1]
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ret %Value %imm_val
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NumberLiteralIntSlow: ; preds = %no_exception7
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%toVal = call %Value @X4( i32 %addconv82 ) ; <%Value> [#uses=1]
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ret %Value %toVal
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}
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