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Fix left shifts of negative values in MipsDisassembler.
This bug was reported by UBSan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216920 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -451,7 +451,7 @@ static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
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InsnType Rs = fieldFromInstruction(insn, 21, 5);
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InsnType Rt = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
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bool HasRs = false;
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if (Rs >= Rt) {
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@ -490,7 +490,7 @@ static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
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InsnType Rs = fieldFromInstruction(insn, 21, 5);
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InsnType Rt = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
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bool HasRs = false;
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if (Rs >= Rt) {
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@ -530,7 +530,7 @@ static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
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InsnType Rs = fieldFromInstruction(insn, 21, 5);
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InsnType Rt = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
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bool HasRs = false;
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if (Rt == 0)
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@ -575,7 +575,7 @@ static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
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InsnType Rs = fieldFromInstruction(insn, 21, 5);
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InsnType Rt = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
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if (Rt == 0)
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return MCDisassembler::Fail;
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@ -617,7 +617,7 @@ static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
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InsnType Rs = fieldFromInstruction(insn, 21, 5);
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InsnType Rt = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
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bool HasRs = false;
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bool HasRt = false;
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@ -666,7 +666,7 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
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InsnType Rs = fieldFromInstruction(insn, 21, 5);
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InsnType Rt = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
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bool HasRs = false;
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if (Rt == 0)
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@ -995,15 +995,15 @@ static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
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break;
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case Mips::LD_H:
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case Mips::ST_H:
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Inst.addOperand(MCOperand::CreateImm(Offset << 1));
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Inst.addOperand(MCOperand::CreateImm(Offset * 2));
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break;
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case Mips::LD_W:
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case Mips::ST_W:
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Inst.addOperand(MCOperand::CreateImm(Offset << 2));
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Inst.addOperand(MCOperand::CreateImm(Offset * 4));
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break;
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case Mips::LD_D:
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case Mips::ST_D:
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Inst.addOperand(MCOperand::CreateImm(Offset << 3));
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Inst.addOperand(MCOperand::CreateImm(Offset * 8));
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break;
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}
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@ -1225,7 +1225,7 @@ static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder) {
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int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4;
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int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
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Inst.addOperand(MCOperand::CreateImm(BranchOffset));
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return MCDisassembler::Success;
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}
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@ -1244,7 +1244,7 @@ static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder) {
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int32_t BranchOffset = SignExtend32<21>(Offset) << 2;
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int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
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Inst.addOperand(MCOperand::CreateImm(BranchOffset));
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return MCDisassembler::Success;
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@ -1254,7 +1254,7 @@ static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder) {
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int32_t BranchOffset = SignExtend32<26>(Offset) << 2;
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int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
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Inst.addOperand(MCOperand::CreateImm(BranchOffset));
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return MCDisassembler::Success;
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@ -1264,7 +1264,7 @@ static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder) {
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int32_t BranchOffset = SignExtend32<16>(Offset) << 1;
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int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
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Inst.addOperand(MCOperand::CreateImm(BranchOffset));
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return MCDisassembler::Success;
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}
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@ -1317,12 +1317,12 @@ static DecodeStatus DecodeExtSize(MCInst &Inst,
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static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
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Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) << 3));
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Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
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return MCDisassembler::Success;
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}
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