6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-17 20:29:31 +00:00
Code Issues Projects Releases Wiki Activity

fix CodeGen/Generic/2008-01-25-dag-combine-mul.ll on sparc, PR2105

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47706 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-02-28 05:44:20 +00:00
parent 48840f8db9
commit 61273d55e9
2 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/Sparc/README.txt
View File

@ -7,6 +7,7 @@ To-do
* We can fold small constant offsets into the %hi/%lo references to constant
pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions. It's
not clear how to write a pattern for this though:

3
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -218,6 +218,9 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
// FIXME: Sparc provides these multiplies, but we don't have them yet.
setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);