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Move all data members to the end of the class.
Add a hook to find out how the target handles shift amounts that are out of range. Either they are undefined (the default), they mask the shift amount to the size of the register (X86, Alpha, etc), or they extend the shift (PPC). This defaults to undefined, which is conservatively correct. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19676 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -43,53 +43,6 @@ namespace llvm {
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/// target-specific constructs to SelectionDAG operators.
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///
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class TargetLowering {
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TargetMachine &TM;
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const TargetData &TD;
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/// IsLittleEndian - True if this is a little endian target.
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///
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bool IsLittleEndian;
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/// PointerTy - The type to use for pointers, usually i32 or i64.
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///
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MVT::ValueType PointerTy;
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/// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
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/// PointerTy is.
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MVT::ValueType ShiftAmountTy;
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/// SetCCResultTy - The type that SetCC operations use. This defaults to the
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/// PointerTy.
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MVT::ValueType SetCCResultTy;
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/// RegClassForVT - This indicates the default register class to use for
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/// each ValueType the target supports natively.
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TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
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unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
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/// ValueTypeActions - This is a bitvector that contains two bits for each
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/// value type, where the two bits correspond to the LegalizeAction enum.
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/// This can be queried with "getTypeAction(VT)".
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unsigned ValueTypeActions;
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/// TransformToType - For any value types we are promoting or expanding, this
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/// contains the value type that we are changing to. For Expanded types, this
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/// contains one step of the expand (e.g. i64 -> i32), even if there are
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/// multiple steps required (e.g. i64 -> i16). For types natively supported
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/// by the system, this holds the same type (e.g. i32 -> i32).
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MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
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/// OpActions - For each operation and each value type, keep a LegalizeAction
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/// that indicates how instruction selection should deal with the operation.
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/// Most operations are Legal (aka, supported natively by the target), but
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/// operations that are not should be described. Note that operations on
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/// non-legal value types are not described here.
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unsigned OpActions[128];
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std::vector<double> LegalFPImmediates;
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std::vector<std::pair<MVT::ValueType,
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TargetRegisterClass*> > AvailableRegClasses;
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public:
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/// LegalizeAction - This enum indicates whether operations are valid for a
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/// target, and if not, what action should be used to make them valid.
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@ -100,6 +53,12 @@ public:
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Custom, // Use the LowerOperation hook to implement custom lowering.
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};
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enum OutOfRangeShiftAmount {
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Undefined, // Oversized shift amounts are undefined (default).
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Mask, // Shift amounts are auto masked (anded) to value size.
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Extend, // Oversized shift pulls in zeros or sign bits.
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};
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TargetLowering(TargetMachine &TM);
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virtual ~TargetLowering();
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@ -110,6 +69,7 @@ public:
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MVT::ValueType getPointerTy() const { return PointerTy; }
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MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
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MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
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OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
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/// getRegClassFor - Return the register class that should be used for the
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/// specified value type. This may only be called on legal types.
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@ -223,6 +183,12 @@ protected:
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/// of a setcc operation. This defaults to the pointer type.
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void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
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/// setShiftAmountFlavor - Describe how the target handles out of range shift
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/// amounts.
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void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
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ShiftAmtHandling = OORSA;
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}
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/// addRegisterClass - Add the specified register class as an available
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/// regclass for the specified value type. This indicates the selector can
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/// handle values of that class natively.
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@ -307,6 +273,58 @@ public:
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/// If the target has no operations that require custom lowering, it need not
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/// implement this. The default implementation of this aborts.
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virtual SDOperand LowerOperation(SDOperand Op);
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private:
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TargetMachine &TM;
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const TargetData &TD;
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/// IsLittleEndian - True if this is a little endian target.
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///
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bool IsLittleEndian;
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/// PointerTy - The type to use for pointers, usually i32 or i64.
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///
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MVT::ValueType PointerTy;
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/// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
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/// PointerTy is.
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MVT::ValueType ShiftAmountTy;
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OutOfRangeShiftAmount ShiftAmtHandling;
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/// SetCCResultTy - The type that SetCC operations use. This defaults to the
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/// PointerTy.
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MVT::ValueType SetCCResultTy;
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/// RegClassForVT - This indicates the default register class to use for
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/// each ValueType the target supports natively.
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TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
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unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
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/// ValueTypeActions - This is a bitvector that contains two bits for each
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/// value type, where the two bits correspond to the LegalizeAction enum.
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/// This can be queried with "getTypeAction(VT)".
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unsigned ValueTypeActions;
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/// TransformToType - For any value types we are promoting or expanding, this
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/// contains the value type that we are changing to. For Expanded types, this
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/// contains one step of the expand (e.g. i64 -> i32), even if there are
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/// multiple steps required (e.g. i64 -> i16). For types natively supported
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/// by the system, this holds the same type (e.g. i32 -> i32).
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MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
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/// OpActions - For each operation and each value type, keep a LegalizeAction
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/// that indicates how instruction selection should deal with the operation.
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/// Most operations are Legal (aka, supported natively by the target), but
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/// operations that are not should be described. Note that operations on
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/// non-legal value types are not described here.
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unsigned OpActions[128];
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std::vector<double> LegalFPImmediates;
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std::vector<std::pair<MVT::ValueType,
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TargetRegisterClass*> > AvailableRegClasses;
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};
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} // end llvm namespace
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