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R600/SI: Replace TRI->getRegClass(Reg) with TRI->getPhysRegClass(Reg)

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TRI->getRegClass() takes a register class ID, not a register.  We were
using this incorrectly in a few places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237132 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2015-05-12 14:18:11 +00:00
parent 9cc691fa05
commit 61637f35c3
3 changed files with 11 additions and 7 deletions
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13
lib/Target/R600/SIFixSGPRCopies.cpp
View File

@ -140,7 +140,7 @@ const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromUses(
const TargetRegisterClass *RC
= TargetRegisterInfo::isVirtualRegister(Reg) ?
MRI.getRegClass(Reg) :
TRI->getRegClass(Reg);
TRI->getPhysRegClass(Reg);
RC = TRI->getSubRegClass(RC, SubReg);
for (MachineRegisterInfo::use_instr_iterator
@ -183,10 +183,13 @@ bool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy,
unsigned SrcReg = Copy.getOperand(1).getReg();
unsigned SrcSubReg = Copy.getOperand(1).getSubReg();
const TargetRegisterClass *DstRC
= TargetRegisterInfo::isVirtualRegister(DstReg) ?
MRI.getRegClass(DstReg) :
TRI->getRegClass(DstReg);
if (!TargetRegisterInfo::isVirtualRegister(DstReg)) {
// If the destination register is a physical register there isn't really
// much we can do to fix this.
return false;
}
const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
const TargetRegisterClass *SrcRC;

4
lib/Target/R600/SIFoldOperands.cpp
View File

@ -216,7 +216,7 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
const TargetRegisterClass *UseRC
= TargetRegisterInfo::isVirtualRegister(UseReg) ?
MRI.getRegClass(UseReg) :
TRI.getRegClass(UseReg);
TRI.getPhysRegClass(UseReg);
Imm = APInt(64, OpToFold.getImm());
@ -240,7 +240,7 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
const TargetRegisterClass *DestRC
= TargetRegisterInfo::isVirtualRegister(DestReg) ?
MRI.getRegClass(DestReg) :
TRI.getRegClass(DestReg);
TRI.getPhysRegClass(DestReg);
unsigned MovOp = TII->getMovOpcode(DestRC);
if (MovOp == AMDGPU::COPY)

1
lib/Target/R600/SIRegisterInfo.cpp
View File

@ -347,6 +347,7 @@ const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
assert(!TargetRegisterInfo::isVirtualRegister(Reg));
static const TargetRegisterClass *BaseClasses[] = {
&AMDGPU::M0RegRegClass,
&AMDGPU::VGPR_32RegClass,
&AMDGPU::SReg_32RegClass,
&AMDGPU::VReg_64RegClass,