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https://github.com/c64scene-ar/llvm-6502.git
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Asm output is looking a lot better; not correct for all operands yet though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12143 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -67,6 +67,7 @@ namespace {
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void emitConstantValueOnly(const Constant *CV);
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void emitGlobalConstant(const Constant *CV);
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void printConstantPool(MachineConstantPool *MCP);
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void printOperand(const MachineOperand &MI);
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void printMachineInstruction(const MachineInstr *MI);
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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@ -364,6 +365,44 @@ bool V8Printer::runOnMachineFunction(MachineFunction &MF) {
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return false;
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}
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void V8Printer::printOperand(const MachineOperand &MO) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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if (Value *V = MO.getVRegValueOrNull()) {
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O << "<" << V->getName() << ">";
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return;
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}
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// FALLTHROUGH
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case MachineOperand::MO_MachineRegister:
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if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
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O << "%" << RI.get(MO.getReg()).Name;
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else
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O << "%reg" << MO.getReg();
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return;
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case MachineOperand::MO_SignExtendedImmed:
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case MachineOperand::MO_UnextendedImmed:
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O << (int)MO.getImmedValue();
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return;
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case MachineOperand::MO_PCRelativeDisp: {
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ValueMapTy::const_iterator i = NumberForBB.find(MO.getVRegValue());
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assert (i != NumberForBB.end()
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&& "Could not find a BB in the NumberForBB map!");
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O << ".LBB" << i->second << " # PC rel: " << MO.getVRegValue()->getName();
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return;
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}
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case MachineOperand::MO_GlobalAddress:
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O << Mang->getValueName(MO.getGlobal());
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return;
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case MachineOperand::MO_ExternalSymbol:
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O << MO.getSymbolName();
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return;
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default:
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O << "<unknown operand type>"; return;
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}
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}
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/// printMachineInstruction -- Print out a single SparcV8 LLVM instruction
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/// MI in GAS syntax to the current output stream.
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///
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@ -371,7 +410,29 @@ void V8Printer::printMachineInstruction(const MachineInstr *MI) {
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unsigned Opcode = MI->getOpcode();
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const TargetInstrInfo &TII = TM.getInstrInfo();
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const TargetInstrDescriptor &Desc = TII.get(Opcode);
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O << Desc.Name << "\n"; // not yet done
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O << Desc.Name << " ";
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// print non-immediate, non-register-def operands
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// then print immediate operands
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// then print register-def operands.
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std::vector<MachineOperand> print_order;
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for (unsigned i = 0; i < MI->getNumOperands (); ++i)
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if (!(MI->getOperand (i).isImmediate ()
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|| (MI->getOperand (i).isRegister ()
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&& MI->getOperand (i).isDef ())))
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print_order.push_back (MI->getOperand (i));
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for (unsigned i = 0; i < MI->getNumOperands (); ++i)
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if (MI->getOperand (i).isImmediate ())
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print_order.push_back (MI->getOperand (i));
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for (unsigned i = 0; i < MI->getNumOperands (); ++i)
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if (MI->getOperand (i).isRegister () && MI->getOperand (i).isDef ())
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print_order.push_back (MI->getOperand (i));
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for (unsigned i = 0, e = print_order.size (); i != e; ++i) {
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printOperand (print_order[i]);
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if (i != (print_order.size () - 1))
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O << ", ";
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}
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O << "\n";
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}
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bool V8Printer::doInitialization(Module &M) {
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@ -67,6 +67,7 @@ namespace {
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void emitConstantValueOnly(const Constant *CV);
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void emitGlobalConstant(const Constant *CV);
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void printConstantPool(MachineConstantPool *MCP);
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void printOperand(const MachineOperand &MI);
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void printMachineInstruction(const MachineInstr *MI);
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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@ -364,6 +365,44 @@ bool V8Printer::runOnMachineFunction(MachineFunction &MF) {
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return false;
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}
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void V8Printer::printOperand(const MachineOperand &MO) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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if (Value *V = MO.getVRegValueOrNull()) {
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O << "<" << V->getName() << ">";
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return;
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}
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// FALLTHROUGH
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case MachineOperand::MO_MachineRegister:
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if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
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O << "%" << RI.get(MO.getReg()).Name;
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else
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O << "%reg" << MO.getReg();
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return;
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case MachineOperand::MO_SignExtendedImmed:
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case MachineOperand::MO_UnextendedImmed:
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O << (int)MO.getImmedValue();
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return;
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case MachineOperand::MO_PCRelativeDisp: {
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ValueMapTy::const_iterator i = NumberForBB.find(MO.getVRegValue());
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assert (i != NumberForBB.end()
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&& "Could not find a BB in the NumberForBB map!");
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O << ".LBB" << i->second << " # PC rel: " << MO.getVRegValue()->getName();
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return;
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}
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case MachineOperand::MO_GlobalAddress:
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O << Mang->getValueName(MO.getGlobal());
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return;
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case MachineOperand::MO_ExternalSymbol:
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O << MO.getSymbolName();
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return;
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default:
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O << "<unknown operand type>"; return;
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}
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}
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/// printMachineInstruction -- Print out a single SparcV8 LLVM instruction
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/// MI in GAS syntax to the current output stream.
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///
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@ -371,7 +410,29 @@ void V8Printer::printMachineInstruction(const MachineInstr *MI) {
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unsigned Opcode = MI->getOpcode();
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const TargetInstrInfo &TII = TM.getInstrInfo();
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const TargetInstrDescriptor &Desc = TII.get(Opcode);
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O << Desc.Name << "\n"; // not yet done
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O << Desc.Name << " ";
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// print non-immediate, non-register-def operands
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// then print immediate operands
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// then print register-def operands.
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std::vector<MachineOperand> print_order;
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for (unsigned i = 0; i < MI->getNumOperands (); ++i)
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if (!(MI->getOperand (i).isImmediate ()
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|| (MI->getOperand (i).isRegister ()
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&& MI->getOperand (i).isDef ())))
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print_order.push_back (MI->getOperand (i));
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for (unsigned i = 0; i < MI->getNumOperands (); ++i)
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if (MI->getOperand (i).isImmediate ())
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print_order.push_back (MI->getOperand (i));
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for (unsigned i = 0; i < MI->getNumOperands (); ++i)
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if (MI->getOperand (i).isRegister () && MI->getOperand (i).isDef ())
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print_order.push_back (MI->getOperand (i));
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for (unsigned i = 0, e = print_order.size (); i != e; ++i) {
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printOperand (print_order[i]);
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if (i != (print_order.size () - 1))
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O << ", ";
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}
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O << "\n";
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}
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bool V8Printer::doInitialization(Module &M) {
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