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Add instruction encodings / disassembly support 3r instructions.
It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne
parent
1340833d7c
commit
62b8786d12
@ -132,6 +132,11 @@ static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus Decode3RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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@ -159,11 +164,15 @@ static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
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static DecodeStatus
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Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
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unsigned Combined = fieldFromInstruction(Insn, 6, 5) +
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fieldFromInstruction(Insn, 5, 1) * 5 - 27;
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if (Combined >= 9)
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unsigned Combined = fieldFromInstruction(Insn, 6, 5);
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if (Combined < 27)
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return MCDisassembler::Fail;
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if (fieldFromInstruction(Insn, 5, 1)) {
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if (Combined == 31)
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return MCDisassembler::Fail;
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Combined += 5;
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}
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Combined -= 27;
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unsigned Op1High = Combined % 3;
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unsigned Op2High = Combined / 3;
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Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
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@ -171,15 +180,78 @@ Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
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return MCDisassembler::Success;
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}
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static DecodeStatus
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Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
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unsigned &Op3) {
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unsigned Combined = fieldFromInstruction(Insn, 6, 5);
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if (Combined >= 27)
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return MCDisassembler::Fail;
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unsigned Op1High = Combined % 3;
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unsigned Op2High = (Combined / 3) % 3;
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unsigned Op3High = Combined / 9;
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Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
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Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
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Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
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return MCDisassembler::Success;
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}
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static DecodeStatus
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Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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// Try and decode as a 3R instruction.
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unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
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switch (Opcode) {
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case 0x2:
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Inst.setOpcode(XCore::ADD_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x3:
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Inst.setOpcode(XCore::SUB_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x4:
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Inst.setOpcode(XCore::SHL_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x5:
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Inst.setOpcode(XCore::SHR_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x6:
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Inst.setOpcode(XCore::EQ_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x7:
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Inst.setOpcode(XCore::AND_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x8:
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Inst.setOpcode(XCore::OR_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x9:
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Inst.setOpcode(XCore::LDW_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x10:
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Inst.setOpcode(XCore::LD16S_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x11:
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Inst.setOpcode(XCore::LD8U_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x18:
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Inst.setOpcode(XCore::LSS_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x19:
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Inst.setOpcode(XCore::LSU_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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}
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return MCDisassembler::Fail;
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}
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static DecodeStatus
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Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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}
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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return S;
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}
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@ -188,10 +260,11 @@ DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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}
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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return S;
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}
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@ -200,11 +273,12 @@ Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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}
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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return S;
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}
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@ -213,10 +287,11 @@ DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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Inst.addOperand(MCOperand::CreateImm(Op2));
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}
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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Inst.addOperand(MCOperand::CreateImm(Op2));
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return S;
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}
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@ -225,10 +300,11 @@ DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeBitpOperand(Inst, Op2, Address, Decoder);
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}
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeBitpOperand(Inst, Op2, Address, Decoder);
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return S;
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}
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@ -237,11 +313,12 @@ DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeBitpOperand(Inst, Op2, Address, Decoder);
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}
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeBitpOperand(Inst, Op2, Address, Decoder);
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return S;
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}
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@ -271,6 +348,19 @@ DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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return S;
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}
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static DecodeStatus
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Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2, Op3;
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DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
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}
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return S;
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}
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MCDisassembler::DecodeStatus
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XCoreDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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@ -33,8 +33,10 @@ class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
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// Instruction formats
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//===----------------------------------------------------------------------===//
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class _F3R<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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let Inst{15-11} = opc;
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let DecoderMethod = "Decode3RInstruction";
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}
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class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern>
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@ -200,48 +200,40 @@ def InlineJT32 : Operand<i32> {
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// Three operand short
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multiclass F3R_2RUS<string OpcStr, SDNode OpNode> {
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def _3r: _F3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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def _2rus : _F2RUS<
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(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
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multiclass F3R_2RUS<bits<5> opc, string OpcStr, SDNode OpNode> {
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def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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def _2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
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}
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multiclass F3R_2RUS_np<string OpcStr> {
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def _3r: _F3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[]>;
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def _2rus : _F2RUS<
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(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[]>;
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multiclass F3R_2RUS_np<bits<5> opc, string OpcStr> {
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def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"), []>;
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def _2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"), []>;
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}
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multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> {
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def _3r: _F3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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multiclass F3R_2RBITP<bits<5> opc, string OpcStr, SDNode OpNode> {
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def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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def _2rus : _F2RUS<
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(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
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}
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class F3R<string OpcStr, SDNode OpNode> : _F3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
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_F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
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class F3R_np<string OpcStr> : _F3R<
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(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"),
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[]>;
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class F3R_np<bits<5> opc, string OpcStr> :
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_F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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!strconcat(OpcStr, " $dst, $b, $c"), []>;
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// Three operand long
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/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
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@ -390,46 +382,44 @@ let usesCustomInserter = 1 in {
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//===----------------------------------------------------------------------===//
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// Three operand short
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defm ADD : F3R_2RUS<"add", add>;
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defm SUB : F3R_2RUS<"sub", sub>;
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defm ADD : F3R_2RUS<0b00010, "add", add>;
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defm SUB : F3R_2RUS<0b00011, "sub", sub>;
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let neverHasSideEffects = 1 in {
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defm EQ : F3R_2RUS_np<"eq">;
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def LSS_3r : F3R_np<"lss">;
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def LSU_3r : F3R_np<"lsu">;
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defm EQ : F3R_2RUS_np<0b00110, "eq">;
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def LSS_3r : F3R_np<0b11000, "lss">;
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def LSU_3r : F3R_np<0b11001, "lsu">;
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}
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def AND_3r : F3R<"and", and>;
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def OR_3r : F3R<"or", or>;
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def AND_3r : F3R<0b00111, "and", and>;
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def OR_3r : F3R<0b01000, "or", or>;
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let mayLoad=1 in {
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def LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
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"ldw $dst, $addr[$offset]",
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[]>;
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def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
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(ins GRRegs:$addr, GRRegs:$offset),
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"ldw $dst, $addr[$offset]", []>;
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def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset),
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"ldw $dst, $addr[$offset]",
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[]>;
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def LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
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"ld16s $dst, $addr[$offset]",
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[]>;
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def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
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(ins GRRegs:$addr, GRRegs:$offset),
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"ld16s $dst, $addr[$offset]", []>;
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def LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
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"ld8u $dst, $addr[$offset]",
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[]>;
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def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),
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(ins GRRegs:$addr, GRRegs:$offset),
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"ld8u $dst, $addr[$offset]", []>;
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}
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let mayStore=1 in {
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def STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
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"stw $val, $addr[$offset]",
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[]>;
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def STW_3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
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"stw $val, $addr[$offset]", []>;
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def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
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"stw $val, $addr[$offset]",
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[]>;
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"stw $val, $addr[$offset]", []>;
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}
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defm SHL : F3R_2RBITP<"shl", shl>;
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defm SHR : F3R_2RBITP<"shr", srl>;
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defm SHL : F3R_2RBITP<0b00100, "shl", shl>;
|
||||
defm SHR : F3R_2RBITP<0b00101, "shr", srl>;
|
||||
// TODO tsetr
|
||||
|
||||
// Three operand long
|
||||
|
||||
@ -196,3 +196,41 @@
|
||||
|
||||
# CHECK: settw res[r7], r2
|
||||
0x9b 0xff 0xec 0x27
|
||||
|
||||
# 3r instructions
|
||||
|
||||
# CHECK: add r1, r2, r3
|
||||
0x1b 0x10
|
||||
|
||||
# CHECK: and r11, r10, r9
|
||||
0xb9 0x3e
|
||||
|
||||
# CHECK: eq r6, r1, r2
|
||||
0x66 0x30
|
||||
|
||||
# CHECK: ld16s r8, r3[r4]
|
||||
0xcc 0x82
|
||||
|
||||
# CHECK: ld8u r9, r1[r10]
|
||||
0x16 0x8d
|
||||
|
||||
# CHECK: ldw r9, r4[r5]
|
||||
0x91 0x4b
|
||||
|
||||
# CHECK: lss r7, r3, r0
|
||||
0x7c 0xc0
|
||||
|
||||
# CHECK: lsu r5, r8, r6
|
||||
0x12 0xcc
|
||||
|
||||
# CHECK: or r1, r3, r2
|
||||
0x1e 0x40
|
||||
|
||||
# CHECK: shl r8, r2, r4
|
||||
0xc8 0x22
|
||||
|
||||
# CHECK: shr r9, r7, r1
|
||||
0x5d 0x29
|
||||
|
||||
# CHECK: sub r4, r2, r5
|
||||
0x89 0x1a
|
||||
|
||||
Loading…
Reference in New Issue
Block a user